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Jerome Mitard

Jerome Mitard

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
36
Citations
6245
World Ranking
5300
National Ranking
113

Overview

Jerome Mitard is affiliated with Imec in Belgium and specializes in the field of Engineering, with a specific focus on Electrical and Electronic Engineering. Their research work primarily addresses advancements in semiconductor devices and circuit design, semiconductor materials and devices, as well as integrated circuits and semiconductor failure analysis.

Their range of research topics includes:

  • Advancements in Semiconductor Devices and Circuit Design
  • Semiconductor materials and devices
  • Integrated Circuits and Semiconductor Failure Analysis
  • Thin-Film Transistor Technologies
  • Semiconductor materials and interfaces
  • Ferroelectric and Negative Capacitance Devices
  • Silicon Carbide Semiconductor Technologies

Jerome Mitard has contributed extensively to scholarly literature with multiple papers published in prominent venues. Some of their recent works are:

  • Understanding and modelling the PBTI reliability of thin-film IGZO transistors (2021), published in the 2021 IEEE International Electron Devices Meeting (IEDM)
  • Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling (2020), published in IEEE Transactions on Electron Devices
  • Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond (2021), published in the 2021 IEEE International Electron Devices Meeting (IEDM)
  • Total-Ionizing-Dose Response of Highly Scaled Gate-All-Around Si Nanowire CMOS Transistors (2021), published in IEEE Transactions on Nuclear Science
  • Scaling of double-gated WS2 FETs to sub-5nm physical gate length fabricated in a 300mm FAB (2021), published in the 2021 IEEE International Electron Devices Meeting (IEDM)

Collaboration plays an important role in their research, with frequent co-authors including:

  • Naoto Horiguchi
  • Adrian Chasin
  • En Xia Zhang
  • Ronald D. Schrimpf
  • Robert A. Reed

Their publications are often featured in specialized venues, with multiple contributions to:

  • IEEE Transactions on Electron Devices
  • IEEE Transactions on Nuclear Science
  • 2021 IEEE International Electron Devices Meeting (IEDM)
  • Advanced Intelligent Systems
  • ECS Transactions

Jerome Mitard's work situates them at the intersection of materials science and applied electrical engineering, focusing on innovative semiconductor technologies and transistor scaling challenges relevant to emerging technological nodes.

Best Publications

  • Review on high-k dielectrics reliability issues

    G. Ribes;J. Mitard;M. Denais;S. Bruyere

  • Germanium MOSFET Devices: Advances in Materials Understanding, Process Development, and Electrical Performance

    D. P. Brunco;B. De Jaeger;G. Eneman;J. Mitard

  • Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters

    M. Casse;L. Thevenod;B. Guillaumot;L. Tosti

  • Capacitor-less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM

    A. Belmonte;H. Oh;N. Rassoul;G.L. Donadio

  • Characterization and modeling of hysteresis phenomena in high K dielectrics

    C. Leroux;J. Mitard;G. Ghibaudo;X. Garros

  • Record I ON /I OFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability

    J. Mitard;B. De Jaeger;F.E. Leys;G. Hellings

  • Electrical TCAD Simulations of a Germanium pMOSFET Technology

    Geert Hellings;Geert Eneman;Raymond Krom;B De Jaeger

  • Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs

    J. Franco;B. Kaczer;M. Toledano-Luque;Ph. J. Roussel

  • SiGe Channel Technology: Superior Reliability Toward Ultrathin EOT Devices—Part I: NBTI

    J. Franco;B. Kaczer;P. J. Roussel;J. Mitard

  • An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

    N. Waldron;C. Merckling;W. Guo;P. Ong

  • Challenges and opportunities in advanced Ge pMOSFETs

    E Simoen;J Mitard;Geert Hellings;Geert Eneman

  • Border Traps in Ge/III–V Channel Devices: Analysis and Reliability Aspects

    Eddy Simoen;Dennis Han-Chung Lin;A. Alian;G. Brammertz

  • Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization

    R. Ritzenthaler;H. Mertens;V. Pena;G. Santoro

  • Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution

    D. Lin;G. Brammertz;S. Sioncke;C. Fleischmann

  • The Influence of the Epitaxial Growth Process Parameters on Layer Characteristics and Device Performance in Si-passivated Ge pMOSFETs

    Matty R. Caymax;Frederik Leys;Jerome Mitard;Koen Martens

  • Germanium for advanced CMOS anno 2009: a SWOT analysis

    M. Caymax;G. Eneman;F. Bellenger;C. Merckling

  • Advancing CMOS beyond the Si roadmap with Ge and III/V devices

    M. Heyns;A. Alian;G. Brammertz;M. Caymax

  • Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

    L. Witters;H. Arimura;F. Sebaai;A. Hikavyy

  • Gate-all-around nanowire device and method for manufacturing such a device

    Jerome Mitard

  • Understanding and modelling the PBTI reliability of thin-film IGZO transistors

    Unknown

  • Advancing CMOS beyond the Si roadmap with Ge and III/V devices

    Marc Heyns;Ali Reza Alian;Guy Brammertz;Matty Caymax

  • Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO 2 /HfO 2 pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks

    J. Franco;B. Kaczer;Ph J. Roussel;J. Mitard

  • Geometry Dependence of Total-Dose Effects in Bulk FinFETs

    I. Chatterjee;E. X. Zhang;B. L. Bhuva;R. A. Reed

Frequent Co-Authors

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