The scientist’s investigation covers issues in Optoelectronics, Metal gate, Electrical engineering, Gate dielectric and CMOS. His Optoelectronics research is multidisciplinary, incorporating perspectives in Layer, Gate oxide and Field-effect transistor. His work carried out in the field of CMOS brings together such families of science as PMOS logic, Silicon on insulator, Silicon and NMOS logic.
His High-κ dielectric research includes themes of Silicon-germanium and MOSFET. His Dielectric research includes elements of Tin, Electronic engineering, Semiconductor device and Conductor. Michael P. Chudzik interconnects Resistor, Semiconductor and Capacitor in the investigation of issues within Electronic component.
Michael P. Chudzik mainly investigates Optoelectronics, Metal gate, Layer, Dielectric and Gate dielectric. His Optoelectronics research integrates issues from Electronic engineering, Electrical engineering and Gate oxide. The Metal gate study combines topics in areas such as Field-effect transistor and Logic gate.
His Layer research incorporates elements of Oxide and Metal. His Dielectric research is multidisciplinary, relying on both Tin, Nitride and Analytical chemistry. The Gate dielectric study which covers Semiconductor that intersects with Electrical conductor and Epitaxy.
Michael P. Chudzik mainly focuses on Optoelectronics, Gate oxide, Gate dielectric, Electronic engineering and Layer. His work deals with themes such as Threshold voltage and Metal gate, which intersect with Optoelectronics. His Metal gate research incorporates themes from Silicon and Work function.
His study in Gate oxide is interdisciplinary in nature, drawing from both Field-effect transistor, CMOS and Oxide thin-film transistor. The various areas that he examines in his Electronic engineering study include Substrate, Semiconductor device and Time-dependent gate oxide breakdown. The concepts of his Dielectric study are interwoven with issues in Oxide and Nitride.
His primary areas of study are Optoelectronics, Electronic engineering, Gate oxide, Gate dielectric and Dielectric. His Optoelectronics study integrates concerns from other disciplines, such as Fin and Epitaxy. Michael P. Chudzik studied Electronic engineering and Time-dependent gate oxide breakdown that intersect with Metal gate, Barrier layer and Work function.
His Gate oxide study improves the overall literature in Layer. His studies deal with areas such as Threshold voltage and Electrical engineering as well as Layer. In his research, Equivalent oxide thickness is intimately related to X-ray photoelectron spectroscopy, which falls under the overarching field of Dielectric.
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High density chip carrier with integrated passive devices
Hoodgck M P;Denard R H;Divacaruni R.
(2002)
A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates
S. Zafar;Y.H. Kim;V. Narayanan;C. Cabral.
symposium on vlsi technology (2006)
A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates
S. Zafar;Y.H. Kim;V. Narayanan;C. Cabral.
symposium on vlsi technology (2006)
Structure and method for replacement gate mosfet with self-aligned contact using sacrificial mandrel dielectric
Shahab Siddiqui;Michael P. Chudzik;Carl J. Radens.
(2010)
Structure and method for replacement gate mosfet with self-aligned contact using sacrificial mandrel dielectric
Shahab Siddiqui;Michael P. Chudzik;Carl J. Radens.
(2010)
Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for cmos
Nestor A. Bojarczuk;Michael P. Chudzik;Matthew W. Copel;Supratik Guha.
(2005)
Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for cmos
Nestor A. Bojarczuk;Michael P. Chudzik;Matthew W. Copel;Supratik Guha.
(2005)
método de integração metal-dual e dielétrica-dual para transitores de efeito de campo de metal de alta constante (alto-k) e dispositivo semicondutor
Michael P Chudzik;Rashmi Jha;Ravikumar Ramachandran;Richard S Wise.
(2019)
A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process
X. Chen;S. Samavedam;V. Narayanan;K. Stein.
symposium on vlsi technology (2008)
A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process
X. Chen;S. Samavedam;V. Narayanan;K. Stein.
symposium on vlsi technology (2008)
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