World's Best Scientists 2026 revealed!
Michael P. Chudzik

Michael P. Chudzik

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
38
Citations
4841
World Ranking
4979
National Ranking
1732

Michael P. Chudzik publication distribution in Electronics and Electrical Engineering in 2026

The chart shows the distribution of publications by all Research.com ranked scientists in the field of Electronics and Electrical Engineering in 2026. The highlighted bar marks where Michael P. Chudzik sits on this spectrum.

34–53 publications: 24 scientists 54–73 publications: 52 scientists 74–93 publications: 114 scientists 94–113 publications: 203 scientists 114–133 publications: 269 scientists 134–153 publications: 355 scientists 154–173 publications: 403 scientists 174–193 publications: 445 scientists 194–213 publications: 430 scientists 214–233 publications: 431 scientists 234–253 publications: 399 scientists 254–273 publications: 366 scientists 274–293 publications: 335 scientists 294–313 publications: 300 scientists 314–333 publications: 276 scientists 334–353 publications: 250 scientists 354–373 publications: 214 scientists 374–393 publications: 187 scientists 394–413 publications: 152 scientists 414–433 publications: 169 scientists 434–453 publications: 147 scientists 454–473 publications: 111 scientists 474–493 publications: 117 scientists 494–513 publications: 103 scientists 514–533 publications: 99 scientists 534–553 publications: 92 scientists 554–573 publications: 75 scientists 574–593 publications: 58 scientists 594–613 publications: 69 scientists 614–633 publications: 50 scientists 634–653 publications: 62 scientists 654–673 publications: 54 scientists 674–693 publications: 44 scientists 694–713 publications: 37 scientists 714–733 publications: 28 scientists 734–753 publications: 26 scientists 754–773 publications: 26 scientists 774–793 publications: 19 scientists 794–813 publications: 23 scientists 814–833 publications: 20 scientists 834–853 publications: 16 scientists 854–873 publications: 20 scientists 874–893 publications: 11 scientists 894–913 publications: 11 scientists 914–933 publications: 16 scientists 934–953 publications: 13 scientists 954–973 publications: 10 scientists 974–993 publications: 11 scientists 994–1,013 publications: 9 scientists 1,014–1,033 publications: 9 scientists 1,034–1,053 publications: 10 scientists 1,054–1,064 publications: 6 scientists 1,065+ publications: 99 scientists
34 publications 1,065+

This scientist: 162 publications — 18th percentile

18% of scientists in this discipline score the same or lower.

The last bar groups every scientist with 1,065 publications or more.

Michael P. Chudzik D-index placement in Electronics and Electrical Engineering in 2026

The chart shows the D-index (discipline H-index) distribution of Electronics and Electrical Engineering scientists ranked by Research.com in 2026. The highlighted bar marks where Michael P. Chudzik sits on this spectrum.

30 D-Index: 178 scientists 31 D-Index: 257 scientists 32 D-Index: 263 scientists 33 D-Index: 262 scientists 34 D-Index: 244 scientists 35 D-Index: 236 scientists 36 D-Index: 211 scientists 37 D-Index: 220 scientists 38 D-Index: 214 scientists 39 D-Index: 214 scientists 40 D-Index: 205 scientists 41 D-Index: 187 scientists 42 D-Index: 194 scientists 43 D-Index: 201 scientists 44 D-Index: 155 scientists 45 D-Index: 189 scientists 46 D-Index: 148 scientists 47 D-Index: 160 scientists 48 D-Index: 134 scientists 49 D-Index: 130 scientists 50 D-Index: 141 scientists 51 D-Index: 156 scientists 52 D-Index: 108 scientists 53 D-Index: 130 scientists 54 D-Index: 112 scientists 55 D-Index: 97 scientists 56 D-Index: 111 scientists 57 D-Index: 102 scientists 58 D-Index: 108 scientists 59 D-Index: 120 scientists 60 D-Index: 103 scientists 61 D-Index: 93 scientists 62 D-Index: 92 scientists 63 D-Index: 74 scientists 64 D-Index: 77 scientists 65 D-Index: 73 scientists 66 D-Index: 64 scientists 67 D-Index: 69 scientists 68 D-Index: 60 scientists 69 D-Index: 39 scientists 70 D-Index: 57 scientists 71 D-Index: 59 scientists 72 D-Index: 46 scientists 73 D-Index: 49 scientists 74 D-Index: 38 scientists 75 D-Index: 35 scientists 76 D-Index: 32 scientists 77 D-Index: 35 scientists 78 D-Index: 31 scientists 79 D-Index: 22 scientists 80 D-Index: 34 scientists 81 D-Index: 31 scientists 82 D-Index: 34 scientists 83 D-Index: 23 scientists 84 D-Index: 18 scientists 85 D-Index: 30 scientists 86 D-Index: 19 scientists 87 D-Index: 19 scientists 88 D-Index: 20 scientists 89 D-Index: 8 scientists 90 D-Index: 17 scientists 91 D-Index: 7 scientists 92 D-Index: 14 scientists 93 D-Index: 9 scientists 94 D-Index: 15 scientists 95 D-Index: 10 scientists 96 D-Index: 12 scientists 97 D-Index: 10 scientists 98 D-Index: 10 scientists 99 D-Index: 12 scientists 100 D-Index: 16 scientists 101 D-Index: 5 scientists 102 D-Index: 7 scientists 103 D-Index: 7 scientists 104 D-Index: 8 scientists 105 D-Index: 9 scientists 106 D-Index: 13 scientists 107 D-Index: 4 scientists 108 D-Index: 5 scientists 109 D-Index: 10 scientists 110 D-Index: 8 scientists 111+ D-Index: 96 scientists
30 D-Index 111+

This scientist: 38 D-Index — 30th percentile

30% of scientists in this discipline score the same or lower.

The last bar groups every scientist with 111 D-Index or more.

Overview

What is he best known for?

The fields of study he is best known for:

  • Semiconductor
  • Electrical engineering
  • Transistor

The scientist’s investigation covers issues in Optoelectronics, Metal gate, Electrical engineering, Gate dielectric and CMOS. His Optoelectronics research is multidisciplinary, incorporating perspectives in Layer, Gate oxide and Field-effect transistor. His work carried out in the field of CMOS brings together such families of science as PMOS logic, Silicon on insulator, Silicon and NMOS logic.

His High-κ dielectric research includes themes of Silicon-germanium and MOSFET. His Dielectric research includes elements of Tin, Electronic engineering, Semiconductor device and Conductor. Michael P. Chudzik interconnects Resistor, Semiconductor and Capacitor in the investigation of issues within Electronic component.

His most cited work include:

  • High density chip carrier with integrated passive devices (274 citations)
  • A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates (171 citations)
  • Structure and method for replacement gate mosfet with self-aligned contact using sacrificial mandrel dielectric (166 citations)

What are the main themes of his work throughout his whole career to date?

Michael P. Chudzik mainly investigates Optoelectronics, Metal gate, Layer, Dielectric and Gate dielectric. His Optoelectronics research integrates issues from Electronic engineering, Electrical engineering and Gate oxide. The Metal gate study combines topics in areas such as Field-effect transistor and Logic gate.

His Layer research incorporates elements of Oxide and Metal. His Dielectric research is multidisciplinary, relying on both Tin, Nitride and Analytical chemistry. The Gate dielectric study which covers Semiconductor that intersects with Electrical conductor and Epitaxy.

He most often published in these fields:

  • Optoelectronics (74.67%)
  • Metal gate (42.00%)
  • Layer (39.33%)

What were the highlights of his more recent work (between 2012-2016)?

  • Optoelectronics (74.67%)
  • Gate oxide (30.67%)
  • Gate dielectric (36.67%)

In recent papers he was focusing on the following fields of study:

Michael P. Chudzik mainly focuses on Optoelectronics, Gate oxide, Gate dielectric, Electronic engineering and Layer. His work deals with themes such as Threshold voltage and Metal gate, which intersect with Optoelectronics. His Metal gate research incorporates themes from Silicon and Work function.

His study in Gate oxide is interdisciplinary in nature, drawing from both Field-effect transistor, CMOS and Oxide thin-film transistor. The various areas that he examines in his Electronic engineering study include Substrate, Semiconductor device and Time-dependent gate oxide breakdown. The concepts of his Dielectric study are interwoven with issues in Oxide and Nitride.

Between 2012 and 2016, his most popular works were:

  • Replacement Gate With Reduced Gate Leakage Current (42 citations)
  • Challenges of nickel silicidation in CMOS technologies (23 citations)
  • FIN Field Effect Transistors Having Multiple Threshold Voltages (23 citations)

In his most recent research, the most cited papers focused on:

  • Semiconductor
  • Electrical engineering
  • Integrated circuit

His primary areas of study are Optoelectronics, Electronic engineering, Gate oxide, Gate dielectric and Dielectric. His Optoelectronics study integrates concerns from other disciplines, such as Fin and Epitaxy. Michael P. Chudzik studied Electronic engineering and Time-dependent gate oxide breakdown that intersect with Metal gate, Barrier layer and Work function.

His Gate oxide study improves the overall literature in Layer. His studies deal with areas such as Threshold voltage and Electrical engineering as well as Layer. In his research, Equivalent oxide thickness is intimately related to X-ray photoelectron spectroscopy, which falls under the overarching field of Dielectric.

Best Publications

  • A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates

    S. Zafar;Y.H. Kim;V. Narayanan;C. Cabral

  • Structure and method for replacement gate mosfet with self-aligned contact using sacrificial mandrel dielectric

    Shahab Siddiqui;Michael P. Chudzik;Carl J. Radens

  • Charge transport, optical transparency, microstructure, and processing relationships in transparent conductive indium-zinc oxide films grown by low-pressure metal-organic chemical vapor deposition

    Anchuan Wang;Jiyan Dai;Jizhi Cheng;Michael P. Chudzik

  • A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

    X. Chen;S. Samavedam;V. Narayanan;K. Stein

  • Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for cmos

    Nestor A. Bojarczuk;Michael P. Chudzik;Matthew W. Copel;Supratik Guha

  • A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

    S. Krishnan;U. Kwon;N. Moumen;M.W. Stoker

  • método de integração metal-dual e dielétrica-dual para transitores de efeito de campo de metal de alta constante (alto-k) e dispositivo semicondutor

    Michael P Chudzik;Rashmi Jha;Ravikumar Ramachandran;Richard S Wise

  • Sige channel epitaxial development for high-k PFET manufacturability

    Michael P. Chudzik;Dominic J. Schepis;Linda Black

  • High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

    M. Chudzik;B. Doris;R. Mo;J. Sleight

  • Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

    V. Narayanan;V.K. Paruchuri;N.A. Bojarczuk;B.P. Linder

  • 22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

    S. Narasimha;P. Chang;C. Ortolland;D. Fried

  • Method for forming a uniform distribution of nitrogen in silicon oxynitride gate dielectric

    Anthony I. Chou;Michael P. Chudzik;Toshiharu Furukawa;Oleg Gluschenkov

  • Scaling the MOSFET gate dielectric: From high-k to higher-k? (Invited Paper)

    Martin M. Frank;SangBum Kim;Stephen L. Brown;John Bruley

  • High performance CMOS circuits, and methods for fabricating same

    John C. Arnold;Glenn A. Biery;Alessandro C. Callegari;Tze-Chiang Chen

  • On the integration of CMOS with hybrid crystal orientations

    M. Yang;V. Chan;S.H. Ku;M. Ieong

  • Replacement Gate With Reduced Gate Leakage Current

    Takashi Ando;Michael P. Chudzik;Rishikesh Krishnan;Siddarth A. Krishnan

  • Scaling deep trench based eDRAM on SOI to 32nm and Beyond

    G. Wang;D. Anand;N. Butt;A. Cestero

  • Thermally robust dual-work function ALD-MN/sub x/ MOSFETs using conventional CMOS process flow

    D.-G. Park;Z.J. Luo;N. Edleman;W. Zhu

  • High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper

    B. Greene;Q. Liang;K. Amarnath;Y. Wang

  • Method and structure for gate height scaling with high-k/metal gate technology

    Michael P. Chudzik;Ricardo A. Donaton;William K. Henson;Yue Liang

  • Inversion channel mobility in high-/spl kappa/ high performance MOSFETs

    Z. Ren;M.V. Fischetti;E.P. Gusev;E.A. Cartier

Frequent Co-Authors

Vijay Narayanan
Vijay Narayanan IBM (United States)
Vamsi K. Paruchuri
Vamsi K. Paruchuri IBM (United States)
Bruce B. Doris
Bruce B. Doris IBM (United States)
Eduard A. Cartier
Eduard A. Cartier IBM (United States)
Martin M. Frank
Martin M. Frank IBM (United States)
Oleg Gluschenkov
Oleg Gluschenkov IBM (United States)
Sufi Zafar
Sufi Zafar IBM (United States)
Supratik Guha
Supratik Guha Argonne National Laboratory
Carl J. Radens
Carl J. Radens IBM (United States)
James H. Stathis
James H. Stathis IBM (United States)

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