World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
44
Citations
7510
World Ranking
3752
National Ranking
1353

Overview

What is he best known for?

The fields of study he is best known for:

  • Electrical engineering
  • Integrated circuit
  • Semiconductor

His scientific interests lie mostly in Optoelectronics, Electrical engineering, Layer, Transistor and Substrate. His studies deal with areas such as Semiconductor device, Trench, Electrical conductor, Gate dielectric and Gate oxide as well as Optoelectronics. Carl J. Radens has researched Trench in several fields, including Etching and Geotechnical engineering.

As a part of the same scientific study, Carl J. Radens usually deals with the Electrical engineering, concentrating on Silicon on insulator and frequently concerns with Static random-access memory, Integrated circuit and Epitaxy. His Transistor research incorporates themes from Electronic engineering and Dynamic random-access memory. His research in Substrate intersects with topics in Silicon, Wafer, Dopant and Flash memory.

His most cited work include:

  • Intelligent wireless power charging system (218 citations)
  • Challenges and future directions for the scaling of dynamic random-access memory (DRAM) (216 citations)
  • Structure and method for replacement gate mosfet with self-aligned contact using sacrificial mandrel dielectric (166 citations)

What are the main themes of his work throughout his whole career to date?

His primary areas of study are Optoelectronics, Electrical engineering, Trench, Capacitor and Layer. The study incorporates disciplines such as Transistor, Substrate and Electronic engineering in addition to Optoelectronics. His Transistor course of study focuses on Silicon on insulator and Insulator.

His Electrical engineering study combines topics in areas such as Dram and Conductor. His study explores the link between Trench and topics such as Etching that cross with problems in Substrate. His biological study spans a wide range of topics, including Structural engineering, Doping and Integrated circuit.

He most often published in these fields:

  • Optoelectronics (67.44%)
  • Electrical engineering (38.76%)
  • Trench (32.30%)

What were the highlights of his more recent work (between 2011-2021)?

  • Optoelectronics (67.44%)
  • Layer (24.03%)
  • Integrated circuit (14.73%)

In recent papers he was focusing on the following fields of study:

Carl J. Radens mainly focuses on Optoelectronics, Layer, Integrated circuit, Electronic engineering and Dielectric. His Optoelectronics research integrates issues from Substrate, Semiconductor device, Interconnection and Electrical engineering. His Layer study combines topics from a wide range of disciplines, such as Transistor and Structural engineering.

His Transistor research incorporates elements of Electrical contacts, Electrical conductor and Silicon. In Integrated circuit, he works on issues like Die, which are connected to Hard mask. His Electronic engineering research is multidisciplinary, incorporating elements of Electronic circuit, Capacitance, Metal, Etching and Insulator.

Between 2011 and 2021, his most popular works were:

  • Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts (44 citations)
  • Self-aligned via interconnect structures (29 citations)
  • Integration of fin-based devices and etsoi devices (28 citations)

In his most recent research, the most cited papers focused on:

  • Electrical engineering
  • Semiconductor
  • Integrated circuit

Carl J. Radens mainly investigates Optoelectronics, Layer, Dielectric, Electrical engineering and Gate oxide. Carl J. Radens combines subjects such as Transistor, Substrate, Trench and Epitaxy with his study of Optoelectronics. His Transistor research focuses on subjects like Electrical conductor, which are linked to Chemical-mechanical planarization and Plating.

The Trench study combines topics in areas such as Electronic engineering and Back end of line. As a member of one scientific family, Carl J. Radens mostly works in the field of Layer, focusing on Structural engineering and, on occasion, Interconnection. His study looks at the relationship between Gate oxide and topics such as Gate dielectric, which overlap with Threshold voltage, Nitriding, High-κ dielectric and CMOS.

Best Publications

  • Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

    J. A. Mandelman;R. H. Dennard;G. B. Bronner;J. K. DeBrosse

  • Intelligent wireless power charging system

    Lawrence Clevenger;Timothy Dalton;Louis Hsu;Carl Radens

  • VERTICAL MOSFET SRAM CELL WITH SURROUNDED GATE TO OBTAIN IMPROVED TRANSCONDUCTANCE AND EFFICIENCY

    Hsu Louis L;Gluschenenkov Oleg;Mandelman Jack A;Radens Carl J

  • Structure and method for replacement gate mosfet with self-aligned contact using sacrificial mandrel dielectric

    Shahab Siddiqui;Michael P. Chudzik;Carl J. Radens

  • Fluctuation limits & scaling opportunities for CMOS SRAM cells

    A. Bhavnagarwala;S. Kosonocky;C. Radens;K. Stawiasz

  • Silicon-on-insulator vertical array device trench capacitor DRAM

    Carl J. Radens;Gary B. Bronner;Tze-Chiang Chen;Bijan Davari

  • High performance 14nm SOI FinFET CMOS technology with 0.0174µm 2 embedded DRAM and 15 levels of Cu metallization

    C-H. Lin;B. Greene;S. Narasimha;J. Cai

  • Integrated chip having SRAM, DRAM and Flash memory and method for fabricating the same

    Louis L. Hsu;Carl Radens;Li-Kong Wang

  • Method for trench capacitor dram cell without floating-well effects

    Jack A. Mandelman;Ramachandra Divakaruni;Carl J. Radens;Stephan Kudelka

  • A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

    A.J. Bhavnagarwala;S. Kosonocky;C. Radens;Yuen Chan

  • A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

    Harold Pilo;Igor Arsovski;Kevin Batson;Geordie Braceras

  • Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain

    Dureseti Chidambarrao;Anda C. Mocuta;Dan M. Mocuta;Carl Radens

  • Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same

    Lawrence Clevenger;Timothy Joseph Dalton;Louis Hsu;Carl Radens

  • Method of integrating volatile and non-volatile memory devices in a single chip

    Hsu Louis L;Radens Carl J;Wang Li-Kong

  • High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

    E. Leobandung;H. Nayakama;D. Mocuta;K. Miyamoto

  • High performance FET with elevated source/drain region

    Rama Divakaruni;Louis C. Hsu;Rajiv V. Joshi;Carl J. Radens

  • Structure and method for MOSFET with metallic gate electrode

    Jack A. Mandelman;Oleg Gluschenkov;Carl J. Radens

  • Properties of four-layer planar optical waveguides near cutoff

    W. Borland;D. Zelmon;C. Radens;J. Boyd

  • Replacement gate mosfet with self-aligned diffusion contact

    Sameer H. Jain;Carl J. Radens;Shahab Siddiqui;Jay W. Strane

  • Integrated circuit using damascene gate structure

    Carl Radens;Mary E. Weybright;Gary Bronner

Frequent Co-Authors

Jack A. Mandelman
Jack A. Mandelman Independent Scientist / Consultant, US
Louis L. Hsu
Louis L. Hsu IBM (United States)
William R. Tonti
William R. Tonti Institute of Electrical and Electronics Engineers
Kangguo Cheng
Kangguo Cheng IBM (United States)
Jeffrey P. Gambino
Jeffrey P. Gambino ON Semiconductor (United States)
Dureseti Chidambarrao
Dureseti Chidambarrao IBM (United States)
Oleg Gluschenkov
Oleg Gluschenkov IBM (United States)
Bruce B. Doris
Bruce B. Doris IBM (United States)
Toshiharu Furukawa
Toshiharu Furukawa IBM (United States)
Michael P. Chudzik
Michael P. Chudzik IBM (United States)

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