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Electronics and Electrical Engineering

D-Index
56
Citations
9149
World Ranking
2123
National Ranking
29

Overview

Hang-Ting Lue is affiliated with Macronix International in Taiwan and focuses primarily on engineering, particularly within electrical and electronic engineering. Their research spans a range of topics related to semiconductor devices and advanced memory technologies.

The main topics of their work include:

  • Semiconductor materials and devices
  • Advanced Memory and Neural Computing
  • Ferroelectric and Negative Capacitance Devices
  • Electronic and Structural Properties of Oxides
  • Advancements in Semiconductor Devices and Circuit Design
  • Advanced Data Storage Technologies
  • Advanced Neural Network Applications

Their frequent co-authors comprise researchers involved in related fields, including:

  • Keh-Chung Wang
  • Tzu-Hsuan Hsu
  • Teng-Hao Yeh
  • Chih-Yuan Lu
  • Wei-Chen Chen

Hang-Ting Lue has published in several key venues, particularly those related to electron devices and semiconductor research. Frequent publication venues include:

  • 2022 International Electron Devices Meeting (IEDM)
  • 2021 IEEE International Electron Devices Meeting (IEDM)
  • IEEE Transactions on Electron Devices
  • 2022 IEEE International Reliability Physics Symposium (IRPS)
  • Extended Abstracts of the 2020 International Conference on Solid State Devices and Materials

Recent notable papers by Hang-Ting Lue include:

  • Analog Computing in Memory (CIM) Technique for General Matrix Multiplication (GEMM) to Support Deep Neural Network (DNN) and Cosine Similarity Search Computing using 3D AND-type NOR Flash Devices, 2022, 2022 International Electron Devices Meeting (IEDM)
  • First Theoretical Modeling of the Bandgap-Engineered Oxynitride Tunneling Dielectric for 3D Flash Memory Devices Starting from the Ab Initio Calculation of the Band Diagram to Understand the Programming, Erasing and Reliability, 2021, 2021 IEEE International Electron Devices Meeting (IEDM)
  • A 3D Stackable DRAM: Capacitor-less Three-Wordline Gate-Controlled Thyristor (GCT) RAM with >40 μA Current Sensing Window, >1010 Endurance, and 3-second Retention at Room Temperature, 2022, 2022 International Electron Devices Meeting (IEDM)
  • A Comprehensive Study of Double-Density Hemi-Cylindrical (HC) 3-D NAND Flash, 2020, IEEE Transactions on Electron Devices
  • A Novel Confined Nitride-Trapping Layer Device for 3-D NAND Flash With Robust Retention Performances, 2020, IEEE Transactions on Electron Devices

Best Publications

  • A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device

    Hang-Ting Lue;Tzu-Hsuan Hsu;Yi-Hsuan Hsiao;S. P. Hong

  • Integrated circuit self aligned 3D memory array and manufacturing method

    Hang Ting Lue

  • Memory device, manufacturing method and operating method of the same

    Hang-Ting Lue;Shih-Hung Chen

  • Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays

    Szu Yu Wang;Hang-Ting Lue

  • Integrated circuit 3D memory array and manufacturing method

    Hsiang-Lan Lung;Hang-Ting Lue

  • BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability

    Hang-Ting Lue;Szu-Yu Wang;Erh-Kun Lai;Yen-Hao Shih

  • 3d memory array arranged for fn tunneling program and erase

    Hsiang-Lan Lung;Yen-Hao Shih;Erh-Kun Lai;Ming Hsiu Lee

  • Cell operation methods using gate-injection for floating gate nand flash memory

    Hang-Ting Lue;Tzu-Hsuan Hsu;Erh-Kun Lai

  • Device modeling of ferroelectric memory field-effect transistor (FeMFET)

    Hang-Ting Lue;Chien-Jang Wu;Tseung-Yuen Tseng

  • A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory

    Erh-Kun Lai;Hang-Ting Lue;Yi-Hsuan Hsiao;Jung-Yu Hsieh

  • Memory architecture of 3D array with diode in memory string

    Chun-Hsiung Hung;Shin-Jang Shen;Hang-Ting Lue

  • Non-volatile memory device with a threshold voltage change rate controlled by gate oxide phase

    Sheng-Chih Lai;Hang-Ting Lue

  • Study of sub-30nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application

    Tzu-Hsuan Hsu;Hang-Ting Lue;Chih-Chang Hsieh;Erh-Kun Lai

  • Integrated circuit having capacitor with 3D NAND memory and manufacturing method thereof

    Hang-Ting Lue;Teng-Hao Yeh

  • A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

    Chih-Ping Chen;Hang-Ting Lue;Kuo-Pin Chang;Yi-Hsuan Hsiao

  • Operation scheme with charge balancing erase for charge trapping non-volatile memory

    Hang-Ting Lue;Yen-Hao Shih;Kuang Yeu Hsieh

  • A highly scalable vertical gate (VG) 3D NAND Flash with robust program disturb immunity using a novel PN diode decoding structure

    Chun-Hsiung Hung;Hang-Ting Lue;Kuo-Pin Chang;Chih-Ping Chen

  • Operation scheme for spectrum shift in charge trapping non-volatile memory

    Hang-Ting Lue;Yen-Hao Shih;Kuang Yeu Hsieh;Ming-Hsiu Lee

  • Methods of operating non-volatile memory devices

    Hang-Ting Lue

  • 3D independent double gate flash memory on bounded conductor layer

    Hang-Ting Lue

Frequent Co-Authors

Chih-Yuan Lu
Chih-Yuan Lu Macronix International (Taiwan)
Erh-Kun Lai
Erh-Kun Lai Macronix International (Taiwan)
Ya-Chin King
Ya-Chin King National Tsing Hua University
Hsiang-Lan Lung
Hsiang-Lan Lung Macronix International (Taiwan)
Meng-Fan Chang
Meng-Fan Chang National Tsing Hua University
Tuo-Hung Hou
Tuo-Hung Hou National Yang Ming Chiao Tung University

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