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J. Van Houdt

J. Van Houdt

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
33
Citations
4699
World Ranking
6058
National Ranking
128

Overview

J. Van Houdt is a researcher affiliated with Imec in Belgium specializing in Engineering and Materials Science, with a focus on Electrical and Electronic Engineering and Materials Chemistry. Their scholarly work spans numerous topics related to semiconductor technologies and advanced memory devices.

Their research portfolio covers specific themes, including:

  • Ferroelectric and Negative Capacitance Devices
  • Semiconductor materials and devices
  • Advanced Memory and Neural Computing
  • MXene and MAX Phase Materials
  • Ferroelectric and Piezoelectric Materials
  • Phase-change materials and chalcogenides
  • Thin-Film Transistor Technologies

Recent notable publications from J. Van Houdt include:

  • Investigation of Imprint in FE-HfO₂ and Its Recovery, 2020, IEEE Transactions on Electron Devices
  • Electrical Investigation of Wake-Up in High Endurance Fatigue-Free La and Y Doped HZO Metal-Ferroelectric-Metal Capacitors, 2022, IEEE Transactions on Electron Devices
  • High performance La-doped HZO based ferroelectric capacitors by interfacial engineering, 2022, 2022 International Electron Devices Meeting (IEDM)
  • High-Endurance Ferroelectric (La, Y) and (La, Gd) Co-Doped Hafnium Zirconate Grown by Atomic Layer Deposition, 2022, ACS Applied Electronic Materials
  • Capacitive Memory Window With Non-Destructive Read in Ferroelectric Capacitors, 2023, IEEE Electron Device Letters

J. Van Houdt frequently publishes in the following venues:

  • IEEE Transactions on Electron Devices
  • IEEE Electron Device Letters
  • Applied Physics Letters
  • physica status solidi (RRL) - Rapid Research Letters
  • Solid-State Electronics

Their collaborative network includes frequent coauthors such as:

  • Gouri Sankar Kar
  • M. Popovici
  • N. Ronchi
  • Sergiu Clima
  • Kaustuv Banerjee

J. Van Houdt's expertise typically encompasses advanced device engineering and materials chemistry within the scope of ferroelectric materials and semiconductor device technologies. Their work addresses challenges in memory technologies, including fatigue-free capacitor materials and novel ferroelectric thin films, contributing to the development of electronic devices with improved endurance and performance.

Best Publications

  • High-k dielectrics for future generation memory devices (Invited Paper)

    J. A. Kittl;K. Opsomer;M. Popovici;N. Menou

  • VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices

    B. Govoreanu;P. Blomme;M. Rosmeulen;J. Van Houdt

  • Vertical Ferroelectric HfO 2 FET based on 3-D NAND Architecture: Towards Dense Low-Power Memory

    K. Florent;M. Pesic;A. Subirats;K. Banerjee

  • Analysis of the enhanced hot-electron injection in split-gate transistors useful for EEPROM applications

    J. Van Houdt;P. Heremans;L. Deferm;G. Groeseneken

  • Trap Spectroscopy by Charge Injection and Sensing (TSCIS): A quantitative electrical technique for studying defects in dielectric stacks

    R. Degraeve;M. Cho;B. Govoreanu;B. Kaczer

  • Analytical percolation model for predicting anomalous charge loss in flash memories

    R. Degraeve;F. Schuler;B. Kaczer;M. Lorenzini

  • HIM0S-a high efficiency flash E/sup 2/PROM cell for embedded memory applications

    J. Van Houdt;L. Haspeslagh;D. Wellekens;L. Deferm

  • Write/erase cycling endurance of memory cells with SiO/sub 2//HfO/sub 2/ tunnel dielectric

    P. Blomme;J. Van Houdt;Kristin De Meyer

  • Scaling down the interpoly dielectric for next generation Flash memory: Challenges and opportunities

    B. Govoreanu;D.P. Brunco;J. Van Houdt

  • Understanding ferroelectric Al:HfO2 thin films with Si-based electrodes for 3D applications

    K. Florent;S. Lavizzari;M. Popovici;L. Di Piazza

  • Two-Pulse $C$ – $V$ : A New Method for Characterizing Electron Traps in the Bulk of $ \hbox{SiO}_{2}/\hbox{high-}\kappa$ Dielectric Stacks

    W.D. Zhang;B. Govoreanu;X.F. Zheng;D. Ruiz Aguado

  • Multilayer tunneling barriers for nonvolatile memory applications

    P. Blomme;B. Govoreanu;M. Rosmeulen;J. Van Houdt

  • An analytical model for the optimization of source-side injection flash EEPROM devices

    J.F. Van Houdt;G. Groeseneken;H.E. Maes

  • An investigation of the electron tunneling leakage current through ultrathin oxides/high-k gate stacks at inversion conditions

    B. Govoreanu;P. Blomme;K. Henson;J. Van Houdt

  • Simulation of nanofloating gate memory with high-k stacked dielectrics

    B. Govoreanu;P. Blomme;J. Van Houdt;K. De Meyer

  • Analytical model for failure rate prediction due to anomalous charge loss of flash memories

    R. Degraeve;F. Schuler;M. Lorenzini;D. Wellekens

  • A model for tunneling current in multi-layer tunnel dielectrics

    Bogdan Govoreanu;Pieter Blomme;Maarten Rosmeulen;Jan Van Houdt

  • Optimizing the Readout Bias for the Capacitorless 1T Bulk FinFET RAM Cell

    N. Collaert;M. Aoulaiche;M. Rakowski;A. Redolfi

  • A new scalable self-aligned dual-bit split-gate charge-trapping memory device

    L. Breuil;L. Haspeslagh;P. Blomme;D. Wellekens

  • Comprehensive investigation of the impact of lateral charge migration on retention performance of planar and 3D SONOS devices

    A. Maconi;A. Arreghini;C. Monzio Compagnoni;G. Van den bosch

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