Luca Selmi

Research.com Recognitions

• 2015 - IEEE Fellow For research on carrier transport and reliability of semiconductor devices

Overview

Best Publications

• Nanoscale MOS Transistors: Semi-Classical Transport and Applications

  David Esseni;Pierpaolo Palestri;Luca Selmi

  234
  Citations

• Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors

  L. Knoll;Qing-Tai Zhao;A. Nichau;S. Trellenkamp

  227
  Citations

• Physically based modeling of low field electron mobility in ultrathin single- and double-gate SOI n-MOSFETs

  D. Esseni;A. Abramo;L. Selmi;E. Sangiorgi

  206
  Citations

• Understanding quasi-ballistic transport in nano-MOSFETs: part I-scattering in the channel and in the drain

  P. Palestri;D. Esseni;S. Eminente;C. Fiegna

  192
  Citations

• Nanoscale MOS Transistors

  Unknown

  183
  Citations

• Real-time imaging of microparticles and living cells with CMOS nanocapacitor arrays

  C. Laborde;Federico Pittino;H. A. Verhoeven;S. G. Lemay

  167
  Citations

• Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application

  D. Esseni;M. Mastrapasqua;G.K. Celler;C. Fiegna

  158
  Citations

• Multisubband Monte Carlo Study of Transport, Quantization, and Electron-Gas Degeneration in Ultrathin SOI n-MOSFETs

  L. Lucci;P. Palestri;D. Esseni;L. Bergagnini

  148
  Citations

• An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode

  D. Esseni;M. Mastrapasqua;G.K. Celler;C. Fiegna

  145
  Citations

• A TCAD-Based Methodology to Model the Site-Binding Charge at ISFET/Electrolyte Interfaces

  Andrea Bandiziol;Pierpaolo Palestri;Federico Pittino;David Esseni

  125
  Citations

• Strain-Induced Performance Improvements in InAs Nanowire Tunnel FETs

  F. Conzatti;M. G. Pala;D. Esseni;E. Bano

  118
  Citations

• Investigation of the Transport Properties of Silicon Nanowires Using Deterministic and Monte Carlo Approaches to the Solution of the Boltzmann Transport Equation

  M. Lenzi;P. Palestri;E. Gnani;S. Reggiani

  112
  Citations

• Leakage–Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology

  M. Agostinelli;M. Alioto;D. Esseni;L. Selmi

  112
  Citations

• Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture

  R. Nonis;N. Da Dalt;P. Palestri;L. Selmi

  101
  Citations

• Low field mobility of ultra-thin SOI N- and P-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs

  D. Esseni;M. Mastrapasqua;G.K. Celler;F.H. Baumann

  100
  Citations

• A Design Methodology for MOS Current-Mode Logic Frequency Dividers

  R. Nonis;E. Palumbo;P. Palestri;L. Selmi

  92
  Citations

• An improved semi-classical Monte-Carlo approach for nano-scale MOSFET simulation

  P. Palestri;Simone Eminente;D. Esseni;Claudio Fiegna

  91
  Citations

• Impact of TFET Unidirectionality and Ambipolarity on the Performance of 6T SRAM Cells

  Sebastiano Strangio;Pierpaolo Palestri;David Esseni;Luca Selmi

  90
  Citations

• Mobility extraction in SOI MOSFETs with sub 1 nm body thickness

  M. Schmidt;Max C. Lemme;H. D. B. Gottlob;F. Driussi

  89
  Citations

• Demonstration of improved transient response of inverters with steep slope strained Si NW TFETs by reduction of TAT with pulsed I-V and NW scaling

  L. Knoll;Q. T. Zhao;A. Nichau;S. Richter

  88
  Citations

• On the Apparent Mobility in Nanometric n-MOSFETs

  M. Zilli;D. Esseni;P. Palestri;L. Selmi

  78
  Citations

• Understanding quasi-ballistic transport in nano-MOSFETs: part II-Technology scaling along the ITRS

  S. Eminente;D. Esseni;P. Palestri;C. Fiegna

  76
  Citations