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K. De Meyer

K. De Meyer

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
44
Citations
8791
World Ranking
3700
National Ranking
84

Overview

K. De Meyer is a researcher affiliated with KU Leuven in Belgium, specializing in the field of engineering, with a particular focus on electrical and electronic engineering.

Their work spans several interconnected subfields, including:

  • Electrical and Electronic Engineering
  • Atomic and Molecular Physics, and Optics
  • Biomedical Engineering

Their primary research topics cover a variety of areas related to semiconductor technologies and device physics, including:

  • Semiconductor materials and devices
  • Integrated Circuits and Semiconductor Failure Analysis
  • Semiconductor materials and interfaces
  • Advancements in Semiconductor Devices and Circuit Design
  • Nanowire Synthesis and Applications

K. De Meyer has published in recognized journals such as MRS Advances and the Journal of Applied Physics. Some of their recent papers include:

  • "A snapshot review on metal-semiconductor contact exploration for 7-nm CMOS technology and beyond," published in 2022 in MRS Advances
  • "Understanding the factors affecting contact resistance in nanowire field effect transistors (NWFETs) to improve nanoscale contacts for future scaling," published in 2022 in Journal of Applied Physics

The researcher collaborates with several colleagues frequently, with notable co-authors including:

  • Nadine Collaert
  • Hao Yu
  • Marc Schaekers
  • Jean-Luc Everaert
  • Naoto Horiguchi

Best Publications

  • Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs

    G. Katti;M. Stucchi;K. De Meyer;W. Dehaene

  • Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs

    Kuo-Hsing Kao;A. S. Verhulst;W. G. Vandenberghe;B. Soree

  • Analysis of the parasitic S/D resistance in multiple-gate FETs

    A. Dixit;A. Kottantharayil;N. Collaert;M. Goodwin

  • Influence of device engineering on the analog and RF performances of SOI MOSFETs

    V. Kilchytska;A. Neve;L. Vancaillie;D. Levacq

  • Impact ionization in silicon: A review and update

    Unknown

  • VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices

    B. Govoreanu;P. Blomme;M. Rosmeulen;J. Van Houdt

  • Impact of Line-Edge Roughness on FinFET Matching Performance

    E.. Baravelli;A.. Dixit;R.. Rooyackers;M.. Jurczak

  • Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets

    Kuo-Hsing Kao;A. S. Verhulst;W. G. Vandenberghe;B. Soree

  • Passivation of Ge ( 100 ) ∕ GeO2 ∕ high-κ Gate Stacks Using Thermal Oxide Treatments

    F. Bellenger;M. Houssa;A. Delabie;V. Afanasiev

  • Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime

    W.K. Henson;N. Yang;S. Kubicek;E.M. Vogel

  • Record I ON /I OFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability

    J. Mitard;B. De Jaeger;F.E. Leys;G. Hellings

  • Multi-gate devices for the 32 nm technology node and beyond

    N. Collaert;A. De Keersgieter;A. Dixit;I. Ferain

  • FinFET analogue characterization from DC to 110 GHz

    Dimitri Lederer;Valeriya Kilchytska;Tamara Rudenko;Nadine Collaert

  • Impact of LER and Random Dopant Fluctuations on FinFET Matching Performance

    E. Baravelli;M. Jurczak;N. Speciale;K. De Meyer

  • Impact of Donor Concentration, Electric Field, and Temperature Effects on the Leakage Current in Germanium p $+/$ n Junctions

    G. Eneman;M. Wiot;A. Brugere;O.S.I. Casain

  • Tall triple-gate devices with TiN/HfO/sub 2/ gate stack

    N. Collaert;M. Demand;I. Ferain;J. Lisoni

  • Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

    G. Eneman;P. Verheyen;R. Rooyackers;F. Nouri

  • Exploring the limits of stress-enhanced hole mobility

    L. Smith;V. Moroz;G. Eneman;P. Verheyen

  • Quantum Mechanical Performance Predictions of p-n-i-n Versus Pocketed Line Tunnel Field-Effect Transistors

    D. Verreck;A. S. Verhulst;Kuo-Hsing Kao;W. G. Vandenberghe

  • 22.5 A 4×20Gb/s WDM ring-based hybrid CMOS silicon photonics transceiver

    Michal Rakowski;Marianna Pantouvaki;Peter De Heyn;Peter Verheyen

  • Layout impact on the performance of a locally strained PMOSFET

    G. Eneman;P. Verheyen;R. Rooyackers;F. Nouri

  • 3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding

    G. Katti;A. Mercha;J. Van Olmen;C. Huyghebaert

  • FinFET analog characterization from DC to 110 GHz

    Dimitri Lederer;Valeriya Kilchytska;Tamara Rudenko;N. Collaert

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