Optoelectronics, MOSFET, Electrical engineering, Electronic engineering and Transistor are his primary areas of study. K. De Meyer has included themes like PMOS logic, Nanotechnology and Passivation in his Optoelectronics study. His research in MOSFET intersects with topics in Electron mobility, Silicon, Equivalent series resistance, CMOS and Engineering physics.
K. De Meyer has researched Electrical engineering in several fields, including Doping and Quantum tunnelling. The study incorporates disciplines such as Capacitance, Stress and Integrated circuit in addition to Electronic engineering. His research integrates issues of Logic gate and Scaling in his study of Transistor.
His primary areas of study are Optoelectronics, Electrical engineering, MOSFET, Electronic engineering and CMOS. His Optoelectronics research is multidisciplinary, incorporating perspectives in PMOS logic, Transistor and NMOS logic. His Transistor research integrates issues from Node, Indium and Dopant.
His work carried out in the field of MOSFET brings together such families of science as Metal gate, Electron mobility, Equivalent series resistance, Leakage and Threshold voltage. His Electronic engineering research incorporates themes from Capacitance, Integrated circuit, Transconductance and Silicon-germanium. His work on Cmos process as part of general CMOS study is frequently linked to AND gate, bridging the gap between disciplines.
K. De Meyer spends much of his time researching Optoelectronics, Electrical engineering, Electronic engineering, CMOS and Doping. K. De Meyer is interested in Quantum tunnelling, which is a branch of Optoelectronics. When carried out as part of a general Electrical engineering research project, his work on Field-effect transistor and NMOS logic is frequently linked to work in Stack, therefore connecting diverse disciplines of study.
K. De Meyer combines subjects such as Semiconductor device, Capacitance, Through-silicon via, Silicon-germanium and Germanium with his study of Electronic engineering. In CMOS, K. De Meyer works on issues like Microelectromechanical systems, which are connected to Porosity, Seal and Composite material. The concepts of his Doping study are interwoven with issues in Silicon, Sheet resistance, Ohmic contact, Electrical resistivity and conductivity and Density of states.
His main research concerns Optoelectronics, Doping, Electronic engineering, Electrical engineering and Quantum tunnelling. His study in Optoelectronics is interdisciplinary in nature, drawing from both Subthreshold conduction, Temperature measurement and Annealing. His Doping study incorporates themes from PMOS logic, High-electron-mobility transistor and Electrical resistivity and conductivity.
His Electronic engineering study focuses on CMOS in particular. In his study, Wafer, Transconductance, Gate stack and Voltage is inextricably linked to Nanowire, which falls within the broad field of Electrical engineering. His study looks at the relationship between Quantum tunnelling and fields such as Field-effect transistor, as well as how they intersect with chemical problems.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs
G. Katti;M. Stucchi;K. De Meyer;W. Dehaene.
IEEE Transactions on Electron Devices (2010)
Analysis of the parasitic S/D resistance in multiple-gate FETs
A. Dixit;A. Kottantharayil;N. Collaert;M. Goodwin.
IEEE Transactions on Electron Devices (2005)
Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs
Kuo-Hsing Kao;A. S. Verhulst;W. G. Vandenberghe;B. Soree.
IEEE Transactions on Electron Devices (2012)
Influence of device engineering on the analog and RF performances of SOI MOSFETs
V. Kilchytska;A. Neve;L. Vancaillie;D. Levacq.
IEEE Transactions on Electron Devices (2003)
VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices
B. Govoreanu;P. Blomme;M. Rosmeulen;J. Van Houdt.
IEEE Electron Device Letters (2003)
Impact of Line-Edge Roughness on FinFET Matching Performance
E.. Baravelli;A.. Dixit;R.. Rooyackers;M.. Jurczak.
IEEE Transactions on Electron Devices (2007)
Passivation of Ge ( 100 ) ∕ GeO2 ∕ high-κ Gate Stacks Using Thermal Oxide Treatments
F. Bellenger;M. Houssa;A. Delabie;V. Afanasiev.
Journal of The Electrochemical Society (2008)
Record I ON /I OFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability
J. Mitard;B. De Jaeger;F.E. Leys;G. Hellings.
international electron devices meeting (2008)
Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime
W.K. Henson;N. Yang;S. Kubicek;E.M. Vogel.
IEEE Transactions on Electron Devices (2000)
Multi-gate devices for the 32 nm technology node and beyond
N. Collaert;A. De Keersgieter;A. Dixit;I. Ferain.
Solid-state Electronics (2008)
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