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D-Index & Metrics

Electronics and Electrical Engineering

D-Index
34
Citations
10587
World Ranking
5678
National Ranking
1929

Overview

Isabelle Ferain is a researcher affiliated with GlobalFoundries in the United States. Their work primarily spans the field of Engineering, with specific focus areas including Electrical and Electronic Engineering as well as Biomedical Engineering. The main topics of their research encompass advancements in semiconductor devices and circuit design, semiconductor materials and devices, and nanowire synthesis and applications.

The scientist has contributed to the following recent paper:

  • Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion (2020), published in the Journal of Integrated Circuits and Systems

Ferain has frequently published in the Journal of Integrated Circuits and Systems, which is the principal venue associated with their body of work.

Frequent co-authors collaborating with Isabelle Ferain include:

  • Rodrigo T. Doria
  • Marcelo Antonio Pavanello
  • Renan Trevisoli
  • Michelly de Souza
  • Chi-Woo Lee

The focus of their research follows an interdisciplinary approach that integrates device fabrication and performance analysis in semiconductors, particularly exploring the temperature dependence and harmonic distortion characteristics of junctionless transistors. This intersects with their expertise in nanowire technologies and materials science.

Best Publications

  • Nanowire transistors without junctions

    Jean-Pierre Colinge;Chi-Woo Lee;Aryan Afzalian;Aryan Afzalian;Nima Dehdashti Akhavan

  • Junctionless multigate field-effect transistor

    Chi-Woo Lee;Aryan Afzalian;Nima Dehdashti Akhavan;Ran Yan

  • Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

    Isabelle Ferain;Cynthia A. Colinge;Jean-Pierre Colinge

  • Performance estimation of junctionless multigate transistors

    Chi-Woo Lee;Isabelle Ferain;Aryan Afzalian;Ran Yan

  • Junctionless nanowire transistor (JNT): Properties and design guidelines

    A. Kranti;R. Yan;C.-W. Lee;I. Ferain

  • High-Temperature Performance of Silicon Junctionless MOSFETs

    Chi-Woo Lee;A. Borne;I. Ferain;A. Afzalian

  • Reduced electric field in junctionless transistors

    Jean-Pierre Colinge;Chi-Woo Lee;Isabelle Ferain;Nima Dehdashti Akhavan

  • Transport spectroscopy of a single dopant in a gated silicon nanowire.

    H. Sellier;G. P. Lansbergen;J. Caro;S. Rogge

  • Junctionless Multiple-Gate Transistors for Analog Applications

    R. T. Doria;M. A. Pavanello;R. D. Trevisoli;M. de Souza

  • Low subthreshold slope in junctionless multigate transistors

    Chi-Woo Lee;Alexei N. Nazarov;Isabelle Ferain;Nima Dehdashti Akhavan

  • Junctionless nanowire transistor (JNT): Properties and design guidelines

    Unknown

  • SOI gated resistor: CMOS without junctions

    J.P. Colinge;C.W. Lee;A. Afzalian;N. Dehdashti

  • Junctionless Transistors: Physics and Properties

    J. P. Colinge;C. W. Lee;N. Dehdashti Akhavan;R. Yan

  • Multi-gate devices for the 32 nm technology node and beyond

    N. Collaert;A. De Keersgieter;A. Dixit;I. Ferain

  • Errata to “Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors”

    R. D. Trevisoli;R. T. Doria;M. de Souza;S. Das

  • Tall triple-gate devices with TiN/HfO/sub 2/ gate stack

    N. Collaert;M. Demand;I. Ferain;J. Lisoni

  • Multi-gate devices for the 32nm technology node and beyond

    N. Collaert;A. De Keersgieter;A. Dixit;I. Ferain

  • Mobility improvement in nanowire junctionless transistors by uniaxial strain

    Jean-Pierre Raskin;Jean-Pierre Colinge;Isabelle Ferain;Abhinav Kranti

  • Subthreshold channels at the edges of nanoscale triple-gate silicon transistors

    H. Sellier;G. P. Lansbergen;J. Caro;S. Rogge

  • Low temperature germanium to silicon direct wafer bonding using free radical exposure

    Ki Yeol Byun;Isabelle Ferain;Peter G. Fleming;Michael A. Morris

  • Junctionless 6T SRAM cell

    A. Kranti;C.-W. Lee;I. Ferain;R. Yan

  • Sub-threshold channels at the edges of nanoscale triple-gate silicon transistors

    H. Sellier;G. P. Lansbergen;J. Caro;N. Collaert

Frequent Co-Authors

Jean-Pierre Colinge
Jean-Pierre Colinge University of California, Davis
Abhinav Kranti
Abhinav Kranti Indian Institute of Technology Indore
K. De Meyer
K. De Meyer KU Leuven
Luigi Pantisano
Luigi Pantisano Intel (United States)
S. De Gendt
S. De Gendt KU Leuven

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