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Electronics and Electrical Engineering

D-Index
36
Citations
5167
World Ranking
5361
National Ranking
1853

Overview

Luigi Pantisano is affiliated with Intel in the United States. They are involved in research within this organization, contributing to its scientific and technological endeavors.

As of this profile, Luigi Pantisano has not been associated with any listed recent papers, book publications, co-authors, or frequent publication venues. There are no publicly recorded awards attributed to this scientist.

There is also no specific information regarding Luigi Pantisano's main fields of study, subfields, or main research topics based on the available data. This limits the detail available about their academic focus or specialization.

The absence of detailed publication and research data suggests that either the available records are limited, or the scientist's contributions are primarily internal to their affiliation or in areas not widely published in open academic venues.

Best Publications

  • Origin of the threshold voltage instability in SiO 2 /HfO 2 dual layer gate dielectrics

    A. Kerber;E. Cartier;L. Pantisano;R. Degraeve

  • Electrical properties of high-κ gate dielectrics: Challenges, current issues, and possible solutions

    M. Houssa;L. Pantisano;L.-Å. Ragnarsson;R. Degraeve

  • Evidences of oxygen-mediated resistive-switching mechanism in TiN\HfO2\Pt cells

    Ludovic Goux;Piotr Czarnecki;Yang Yin Chen;Luigi Pantisano

  • Characterization of the V/sub T/-instability in SiO/sub 2//HfO/sub 2/ gate dielectrics

    A. Kerber;E. Cartier;L. Pantisano;M. Rosmeulen

  • Passivation and interface state density of SiO2/HfO2-based/polycrystalline-Si gate stacks

    R. J. Carter;E. Cartier;A. Kerber;L. Pantisano

  • $1/f$ Noise in Drain and Gate Current of MOSFETs With High- $k$ Gate Stacks

    P. Magnone;F. Crupi;G. Giusi;C. Pace

  • Record I ON /I OFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability

    J. Mitard;B. De Jaeger;F.E. Leys;G. Hellings

  • On the thermal stability of atomic layer deposited TiN as gate electrode in MOS devices

    J. Westlinder;T. Schram;L. Pantisano;E. Cartier

  • Low-frequency noise behavior of SiO/sub 2/--HfO/sub 2/ dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness

    E. Simoen;A. Mercha;L. Pantisano;C. Claeys

  • On the Gradual Unipolar and Bipolar Resistive Switching of TiN\ HfO2\Pt Memory Systems

    Ludovic Goux;Yang Yin Chen;Luigi Pantisano;Xin Peng Wang

  • Charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes

    A. Kerber;E. Cartier;R. Degraeve;P.J. Roussel

  • Effect of bulk trap density on HfO/sub 2/ reliability and yield

    R. Degraeve;A. Kerber;P. Roussell;E. Cartier

  • Reliability screening of high-k dielectrics based on voltage ramp stress

    Andreas Kerber;Luigi Pantisano;Anabela Veloso;Guido Groeseneken;Guido Groeseneken

  • Estimation of fixed charge densities in hafnium-silicate gate dielectrics

    V.S. Kaushik;B.J. O'Sullivan;G. Pourtois;N. Van Hoornick

  • Characterization of the VT Instability in SiO2/HfO2 Gate Dielectrics

    Andreas Kerber;E Cartier;Luigi Pantisano;Maarten Rosmeulen

  • Charge Trapping and Dielectric Reliability of SiO2/Al2O3 Gate Stacks with TiN Electrodes

    Andreas Kerber;Eduard Cartier;Robin Degraeve;Philippe J. Roussel

  • Intrinsic Switching Behavior in HfO2 RRAM by Fast Electrical Measurements on Novel 2R Test Structures

    A. Fantini;D. J. Wouters;R. Degraeve;L. Goux

  • A study of relaxation current in high-/spl kappa/ dielectric stacks

    Zhen Xu;L. Pantisano;A. Kerber;R. Degraeve

  • Towards understanding degradation and breakdown of SiO 2 /high-k stacks

    T. Kauerauf;R. Degraeve;E. Cartier;B. Govoreanu

  • Roles and Effects of TiN and Pt Electrodes in Resistive-Switching HfO2 Systems

    Ludovic Goux;Xin Peng Wang;Yangyin Chen;Luigi Pantisano

Frequent Co-Authors

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