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D-Index & Metrics

Electronics and Electrical Engineering

D-Index
41
Citations
5776
World Ranking
4348
National Ranking
48

Overview

Mamidala Jagadesh Kumar is affiliated with the Indian Institute of Technology Delhi in India. Their research spans multiple fields, including electrical and electronic engineering, education, computational mechanics, biomedical engineering, and artificial intelligence.

Their scholarly output is notably concentrated in the following subfields:

  • Electrical and Electronic Engineering
  • Education
  • Computational Mechanics
  • Biomedical Engineering
  • Artificial Intelligence

The main topics covered in their work include advancements in semiconductor devices and circuit design, semiconductor materials and devices, online and blended learning, higher education learning practices, global education systems and policies, nanowire synthesis and applications, and integrated circuits and semiconductor failure analysis.

  • Advancements in Semiconductor Devices and Circuit Design
  • Semiconductor materials and devices
  • Online and Blended Learning
  • Higher Education Learning Practices
  • Global Education Systems and Policies
  • Nanowire Synthesis and Applications
  • Integrated Circuits and Semiconductor Failure Analysis

The scientist has published extensively in the following venues:

  • IETE Technical Review
  • IEEE Access
  • Journal of Applied Fluid Mechanics
  • Semiconductor Science and Technology
  • IOP Conference Series Materials Science and Engineering

Recent publications illustrate the diversity of their research interests:

  • "National Education Policy: How does it Affect Higher Education in India?" (2020) - IETE Technical Review
  • "Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study" (2020) - IEEE Access
  • "Artificial Intelligence in Education: Are we ready?" (2023) - IETE Technical Review
  • "What is in store in the January-February 2020 issue of IETE Technical Review?" (2020) - IETE Technical Review
  • "Forging Connections: Integrating Indian Knowledge Systems in Higher Education" (2024) - IETE Technical Review

Collaboration is also evident, with frequent co-authors including Navneet Kaur Saini, Nitish Kumar, Raghvendra Sahai Saxena, Anuj Dhawan, and Aakash Kumar Jain.

Best Publications

  • Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

    A. Chaudhry;M.J. Kumar

  • Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor

    S Saurabh;M J Kumar

  • Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

    M.J. Kumar;A. Chaudhry

  • A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation

    G.V. Reddy;M.J. Kumar

  • Bipolar Charge-Plasma Transistor: A Novel Three Terminal Device

    M. J. Kumar;K. Nadda

  • Fundamentals of Tunnel Field-Effect Transistors

    Sneh Saurabh;Mamidala Jagadesh Kumar

  • Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET

    A. Chaudhry;M.J. Kumar

  • In-Built N + Pocket p-n-p-n Tunnel Field-Effect Transistor

    Dawit Burusie Abdi;Mamidala Jagadesh Kumar

  • Controlling the Drain Side Tunneling Width to Reduce Ambipolar Current in Tunnel FETs Using Heterodielectric BOX

    Shubham Sahay;Mamidala Jagadesh Kumar

  • Nanotube Junctionless FET: Proposal, Design, and Investigation

    Shubham Sahay;Mamidala Jagadesh Kumar

  • Insight into Lateral Band-to-Band-Tunneling in Nanowire Junctionless FETs

    Shubham Sahay;Mamidala Jagadesh Kumar

  • New dual-material SG nanoscale MOSFET: analytical threshold-voltage model

    M.J. Kumar;A.A. Orouji;H. Dhakad

  • Diameter Dependence of Leakage Current in Nanowire Junctionless Field Effect Transistors

    Shubham Sahay;Mamidala Jagadesh Kumar

  • Controlling L-BTBT and Volume Depletion in Nanowire JLFETs Using Core–Shell Architecture

    Shubham Sahay;Mamidala Jagadesh Kumar

  • Junctionless Field-Effect Transistors: Design, Modeling, and Simulation

    Shubham Sahay;Mamidala Jagadesh Kumar

  • Compact Analytical Threshold-Voltage Model of Nanoscale Fully Depleted Strained-Si on Silicon–Germanium-on-Insu lator (SGOI) MOSFETs

    V. Venkataraman;S. Nawal;M.J. Kumar

  • Realizing Efficient Volume Depletion in SOI Junctionless FETs

    Shubham Sahay;Mamidala Jagadesh Kumar

  • Two-dimensional analytical threshold voltage model of nanoscale fully depleted SOI MOSFET with electrically induced S/D extensions

    M.J. Kumar;A.A. Orouji

  • Profile design considerations for minimizing base transit time in SiGe HBT's

    V.S. Patri;M.J. Kumar

  • Spacer Design Guidelines for Nanowire FETs From Gate-Induced Drain Leakage Perspective

    Shubham Sahay;Mamidala Jagadesh Kumar

  • A simple analytical threshold voltage model of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs

    M.J. Kumar;V. Venkataraman;S. Nawal

Frequent Co-Authors

Ali A. Orouji
Ali A. Orouji Semnan University
Sumeet Kumar Gupta
Sumeet Kumar Gupta Purdue University West Lafayette
Meyya Meyyappan
Meyya Meyyappan Ames Research Center
Chongwu Zhou
Chongwu Zhou University of Southern California
Mark Lundstrom
Mark Lundstrom Purdue University West Lafayette
Theodore I. Kamins
Theodore I. Kamins Stanford University
Mark A. Reed
Mark A. Reed Yale University
Kang L. Wang
Kang L. Wang University of California, Los Angeles
Gehan A. J. Amaratunga
Gehan A. J. Amaratunga University of Cambridge
Lars-Erik Wernersson
Lars-Erik Wernersson Lund University

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