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Francois Andrieu

Francois Andrieu

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
40
Citations
7225
World Ranking
4472
National Ranking
79

Overview

Francois Andrieu is affiliated with CEA LETI in France and has a research focus predominantly in the field of engineering, with a specialization in electrical and electronic engineering.

Their work covers several interconnected subfields including materials chemistry, cellular and molecular neuroscience, cognitive neuroscience, and polymers and plastics. The main topics addressed in their research encompass advanced memory and neural computing, ferroelectric and negative capacitance devices, semiconductor materials and devices, phase-change materials and chalcogenides, CCD and CMOS imaging sensors, integrated circuits and semiconductor failure analysis, as well as advancements in semiconductor devices and circuit design.

Francois Andrieu has contributed to publications in a variety of notable scientific venues. These include:

  • IEEE Transactions on Electron Devices
  • Nature Communications
  • Journal of Applied Physics
  • 2021 IEEE International Electron Devices Meeting (IEDM)
  • IEEE Journal of the Electron Devices Society

Their recent published papers feature topics from hardware synapses for neurocomputing to memristor-based neural networks and advanced memory arrays. Selected papers include:

  • A self-adaptive hardware with resistive switching synapses for experience-based neurocomputing, 2023, Nature Communications
  • Powering AI at the edge: A robust, memristor-based binarized neural network with near-memory computing and miniaturized solar cell, 2024, Nature Communications
  • 16kbit HfO2:Si-based 1T-1C FeRAM Arrays Demonstrating High Performance Operation and Solder Reflow Compatibility, 2021, 2021 IEEE International Electron Devices Meeting (IEDM)
  • A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration, 2021, IEEE Transactions on Electron Devices
  • High-Performance Operation and Solder Reflow Compatibility in BEOL-Integrated 16-kb HfO2: Si-Based 1T-1C FeRAM Arrays, 2022, IEEE Transactions on Electron Devices

Throughout their career, they have collaborated frequently with a number of co-authors, including N. Castellani, L. Grenouillet, C. Carabasse, V. Meli, and G. Navarro.

Best Publications

  • Impact of SOI, Si 1-x Ge x OI and GeOI substrates on CMOS compatible Tunnel FET performance

    F. Mayer;C. Le Royer;J.-F. Damlencourt;K. Romanjek

  • Advances, challenges and opportunities in 3D CMOS sequential integration

    P. Batude;M. Vinet;B. Previtali;C. Tabone

  • Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

    O. Faynot;F. Andrieu;O. Weber;C. Fenouillet-Beranger

  • Improved split C-V method for effective mobility extraction in sub-0.1-/spl mu/m Si MOSFETs

    K. Romanjek;F. Andrieu;T. Ernst;G. Ghibaudo

  • High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding

    O. Weber;O. Faynot;F. Andrieu;C. Buj-Dufournet

  • Engineered substrates for future More Moore and More than Moore integrated devices

    L. Clavelier;C. Deguet;L. Di Cioccio;E. Augendre

  • Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters

    M. Casse;L. Thevenod;B. Guillaumot;L. Tosti

  • Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack

    E. Bernard;T. Ernst;B. Guillaumot;N. Vulliet

  • FDSOI devices with thin BOX and ground plane integration for 32 nm node and below

    C. Fenouillet-Beranger;S. Denorme;P. Perreau;C. Buj

  • Engineering strained silicon on insulator wafers with the Smart CutTM technology

    B. Ghyselen;J.-M. Hartmann;T. Ernst;C. Aulnette

  • Performance and design considerations for gate-all-around stacked-NanoWires FETs

    S. Barraud;V. Lapras;B. Previtali;M. P. Samson

  • Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below

    C. Fenouillet-Beranger;P. Perreau;S. Denorme;L. Tosti

  • Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

    F. Andrieu;O. Weber;J. Mazurier;O. Thomas

  • 14nm FDSOI technology for high speed and energy efficient applications

    Olivier Weber;E. Josse;F. Andrieu;A. Cros

  • Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO 2 gate stack

    V. Barral;T. Poiroux;F. Andrieu;C. Buj-Dufournet

  • Nanoscaled MOSFET Transistors on Strained Si, SiGe, Ge Layers: Some Integration and Electrical Properties Features

    Thomas P. Ernst;Francois Andrieu;O. Weber;Jean-Michel Hartmann

  • Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below

    C. Fenouillet-Beranger;P. Perreau;S. Denorme;L. Tosti

  • Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack

    T. Ernst;C. Dupre;C. Isheden;E. Bernard

  • 7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing

    S. Barraud;B. Previtali;C. Vizioz;J.-M. Hartmann

  • Strained tunnel FETs with record I ON : first demonstration of ETSOI TFETs with SiGe channel and RSD

    A. Villalon;C. Le Royer;M. Casse;D. Cooper

  • 3D Sequential Integration: Application-driven technological achievements and guidelines

    P. Batude;L. Brunet;C. Fenouillet-Beranger;F. Andrieu

Frequent Co-Authors

O. Faynot
O. Faynot CEA LETI
Gerard Ghibaudo
Gerard Ghibaudo Grenoble Alpes University
Sorin Cristoloveanu
Sorin Cristoloveanu Grenoble Institute of Technology
Denis Flandre
Denis Flandre Université Catholique de Louvain
Thomas Skotnicki
Thomas Skotnicki Warsaw University of Technology
Jean-Pierre Raskin
Jean-Pierre Raskin Université Catholique de Louvain
P. Paillet
P. Paillet French Alternative Energies and Atomic Energy Commission (CEA)
Sylvain Girard
Sylvain Girard Jean Monnet University

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