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O. Faynot

O. Faynot

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
53
Citations
10599
World Ranking
2415
National Ranking
32

Overview

O. Faynot is affiliated with CEA LETI in France and specializes in engineering, with a particular focus on electrical and electronic engineering. Their research spans advancements in semiconductor devices and circuit design, semiconductor materials and devices, ferroelectric and negative capacitance devices, and radiation effects in electronics.

Their frequently published work appears in notable venues such as IEEE Transactions on Nuclear Science, Solid-State Electronics, and IEEE Transactions on Electron Devices.

Recent research papers by O. Faynot include the following:

  • TID Response of Nanowire Field-Effect Transistors: Impact of the Back-Gate Bias, 2020, IEEE Transactions on Nuclear Science
  • Analysis of electron mobility in 7-level stacked nanosheet GAA nMOSFETs, 2025, Solid-State Electronics
  • Experimental Demonstration of Ω-Gate SOI Nanowire MOS Transistors' Mobility Variation Induced by Substrate Bias, 2022, IEEE Transactions on Electron Devices

Frequent co-authors collaborating with O. Faynot include:

  • Sylvain Barraud
  • M. Vinet
  • Michelly de Souza
  • F. E. Bergamaschi
  • M. Cassé

The main topics addressed in their research are:

  • Advancements in Semiconductor Devices and Circuit Design
  • Semiconductor materials and devices
  • Ferroelectric and Negative Capacitance Devices
  • Radiation Effects in Electronics

Best Publications

  • Advances, challenges and opportunities in 3D CMOS sequential integration

    P. Batude;M. Vinet;B. Previtali;C. Tabone

  • Advances in 3D CMOS sequential integration

    P. Batude;M. Vinet;A. Pouydebasque;C. Le Royer

  • Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

    S. Barraud;M. Berthome;R. Coquand;M. Casse

  • A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration

    A. Hubert;E. Nowak;K. Tachi;V. Maffini-Alvaro

  • Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

    O. Faynot;F. Andrieu;O. Weber;C. Fenouillet-Beranger

  • 3D monolithic integration: Technological challenges and electrical results

    M. Vinet;P. Batude;C. Tabone;B. Previtali

  • CELONCEL: effective design technique for 3-D monolithic integration targeting high performance integrated circuits

    Shashikanth Bobba;Ashutosh Chakraborty;Olivier Thomas;Perrine Batude

  • High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding

    O. Weber;O. Faynot;F. Andrieu;C. Buj-Dufournet

  • Statistical Analysis of the Charge Collected in SOI and Bulk Devices Under Heavy lon and Proton Irradiation—Implications for Digital SETs

    V. Ferlet-Cavrois;P. Paillet;M. Gaillardin;D. Lambert

  • Engineered substrates for future More Moore and More than Moore integrated devices

    L. Clavelier;C. Deguet;L. Di Cioccio;E. Augendre

  • 15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET

    C. Dupre;A. Hubert;S. Becu;M. Jublot

  • 3D monolithic integration

    P. Batude;M. Vinet;A. Pouydebasque;C. Le Royer

  • Multiple gate devices: advantages and challenges

    T. Poiroux;M. Vinet;O. Faynot;J. Widiez

  • FDSOI devices with thin BOX and ground plane integration for 32 nm node and below

    C. Fenouillet-Beranger;S. Denorme;P. Perreau;C. Buj

  • Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

    S. Barraud;R. Coquand;M. Casse;M. Koyama

  • 3DVLSI with CoolCube process: An alternative path to scaling

    P. Batude;C. Fenouillet-Beranger;L. Pasini;V. Lu

  • Direct measurement of transient pulses induced by laser and heavy ion irradiation in deca-nanometer devices

    V. Ferlet-Cavrois;P. Paillet;D. McMorrow;A. Torres

  • GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

    L. Hutin;C. Le Royer;J.-F. Damlencourt;J.-M. Hartmann

  • Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below

    C. Fenouillet-Beranger;P. Perreau;S. Denorme;L. Tosti

  • BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

    S. Khandelwal;Y. S. Chauhan;D. D. Lu;S. Venugopalan

  • Insights on the transient response of fully and partially depleted SOI technologies under heavy-ion and dose-rate irradiations

    V. Ferlet-Cavrois;G. Gasiot;C. Marcandella;C. D'Hose

Frequent Co-Authors

Sorin Cristoloveanu
Sorin Cristoloveanu Grenoble Institute of Technology
Gerard Ghibaudo
Gerard Ghibaudo Grenoble Alpes University
Thomas Skotnicki
Thomas Skotnicki Warsaw University of Technology
Bich-Yen Nguyen
Bich-Yen Nguyen Soitec (France)
P. Paillet
P. Paillet French Alternative Energies and Atomic Energy Commission (CEA)
Denis Flandre
Denis Flandre Université Catholique de Louvain
B. De Salvo
B. De Salvo Meta for Business

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