World's Best Scientists 2026 revealed!

D-Index & Metrics

Computer Science

D-Index
59
Citations
13224
World Ranking
3439
National Ranking
1661

Research.com Recognitions

  • 2001 - ACM Fellow For his outstanding contributions to the fields of test generation and fault simulation of sequential circuits, cache consistency protocols, interconnection networks, and error detection.

Overview

What is he best known for?

The fields of study he is best known for:

  • Operating system
  • Algorithm
  • Programming language

His primary scientific interests are in Parallel computing, Fault coverage, Algorithm, Automatic test pattern generation and Sequential logic. His work on Cache and Multiprocessing as part of general Parallel computing research is often related to Reliability theory, thus linking different fields of science. His Fault coverage study integrates concerns from other disciplines, such as Very-large-scale integration, Testability and Stuck-at fault.

His Algorithm study incorporates themes from Word and Data scrubbing. His work on Test compression as part of general Automatic test pattern generation study is frequently linked to Traverse, therefore connecting diverse disciplines of science. His study in Sequential logic is interdisciplinary in nature, drawing from both Fault Simulator, Genetic algorithm and State.

His most cited work include:

  • HITEC: a test generation package for sequential circuits (625 citations)
  • A low-overhead coherence solution for multiprocessors with private cache memories (444 citations)
  • Test set compaction algorithms for combinational circuits (429 citations)

What are the main themes of his work throughout his whole career to date?

The scientist’s investigation covers issues in Algorithm, Sequential logic, Automatic test pattern generation, Fault coverage and Stuck-at fault. His Algorithm research focuses on Very-large-scale integration and how it connects with Speedup. His biological study spans a wide range of topics, including Genetic algorithm, State, Benchmark, Parallel computing and Fault Simulator.

Janak H. Patel works on Automatic test pattern generation which deals in particular with Test compression. His research on Fault coverage also deals with topics like

  • Electronic engineering which intersects with area such as Digital electronics,
  • Testability which connect with Design for testing and Logic synthesis. His Stuck-at fault research includes elements of Process, Logic simulation, Real-time computing, Fault model and Fault indicator.

He most often published in these fields:

  • Algorithm (40.96%)
  • Sequential logic (34.94%)
  • Automatic test pattern generation (33.73%)

What were the highlights of his more recent work (between 1998-2014)?

  • Algorithm (40.96%)
  • Automatic test pattern generation (33.73%)
  • Test compression (16.87%)

In recent papers he was focusing on the following fields of study:

His main research concerns Algorithm, Automatic test pattern generation, Test compression, Fault coverage and Sequential logic. His Algorithm study incorporates themes from Upper and lower bounds and Benchmark. His studies in Automatic test pattern generation integrate themes in fields like Combinational logic, Very-large-scale integration, Directed graph and Stuck-at fault.

The concepts of his Test compression study are interwoven with issues in Computer hardware, Reduction, Built-in self-test, Scan chain and Test data. His Fault coverage research is multidisciplinary, incorporating perspectives in Overhead and Set. His Sequential logic study combines topics in areas such as State, Fault Simulator, Current, Tree traversal and Test set.

Between 1998 and 2014, his most popular works were:

  • Reducing test application time for full scan embedded cores (331 citations)
  • The effect of a multicomponent multidisciplinary bundle of interventions on sleep and delirium in medical and surgical intensive care patients (148 citations)
  • A case study on the implementation of the Illinois Scan Architecture (128 citations)

In his most recent research, the most cited papers focused on:

  • Operating system
  • Algorithm
  • Programming language

Automatic test pattern generation, Algorithm, Test compression, Test data and Very-large-scale integration are his primary areas of study. The Automatic test pattern generation study combines topics in areas such as Control reconfiguration and Embedded system. In the field of Algorithm, his study on Directed acyclic graph, Graph traversal and Directed graph overlaps with subjects such as Small number and Traverse.

His Test compression study is concerned with the field of Fault coverage as a whole. His Test data research incorporates elements of System testing, Computer engineering and Scan chain, Integrated circuit. The study incorporates disciplines such as Boolean satisfiability problem, Combinational logic, Redundancy and Stuck-at fault in addition to Very-large-scale integration.

Best Publications

  • HITEC: a test generation package for sequential circuits

    Thomas Niermann;Janak H. Patel

  • A low-overhead coherence solution for multiprocessors with private cache memories

    Mark S. Papamarcos;Janak H. Patel

  • Test set compaction algorithms for combinational circuits

    Ilker Hamzaoglu;Janak H. Patel

  • PROOFS: a fast, memory-efficient sequential circuit fault simulator

    T.M. Niermann;Wu-Tung Cheng;J.H. Patel

  • Stride directed prefetching in scalar processors

    John W. C. Fu;Janak H. Patel;Bob L. Janssens

  • Reducing test application time for full scan embedded cores

    I. Hamzaoglu;J.H. Patel

  • New Techniques for Deterministic Test Pattern Generation

    Ilker Hamzaoglu;Janak H. Patel

  • Reliability of scrubbing recovery-techniques for memory systems

    A.M. Saleh;J.J. Serrano;J.H. Patel

  • Sequential Circuit Test Generation in a Genetic Algorithm Framework

    Elizabeth M. Rudnick;Janak H. Patel;Gary S. Greenstein;Thomas M. Niermann

  • Accurate low-cost methods for performance evaluation of cache memory systems

    S. Laha;J.H. Patel;R.K. Iyer

  • Sequential circuit test generation using dynamic state traversal

    Michael S. Hsiao;Elizabeth M. Rudnick;Janak H. Patel

  • Data prefetching in multiprocessor vector cache memories

    John W. C. Fu;Janak H. Patel

  • An optimization based approach to the partial scan design problem

    V. Chickermane;J.H. Patel

  • A case study on the implementation of the Illinois Scan Architecture

    F.F. Hsu;K.M. Butler;J.H. Patel

  • A gate-level simulation environment for alpha-particle-induced transient faults

    Hungse Cha;E.M. Rudnick;J.H. Patel;R.K. Iyer

  • Processor-memory interconnections for multiprocessors

    Janak H. Patel

  • A fault oriented partial scan design approach

    V. Chickermane;J.H. Patel

  • Segment delay faults: a new fault model

    K. Heragu;J.H. Patel;V.D. Agrawal

  • Application of Saluja-Karpovsky compactors to test responses with many unknowns

    J.H. Patel;S.S. Lumetta;S.M. Reddy

  • Error recovery in shared memory multiprocessors using private caches

    K.-L. Wu;W.K. Fuchs;J.H. Patel

Frequent Co-Authors

Michael S. Hsiao
Michael S. Hsiao Virginia Tech
Alok Choudhary
Alok Choudhary Northwestern University
Jacob A. Abraham
Jacob A. Abraham The University of Texas at Austin
W.K. Fuchs
W.K. Fuchs University of Florida
Prithviraj Banerjee
Prithviraj Banerjee Ansys (United States)
Vishwani D. Agrawal
Vishwani D. Agrawal Auburn University
Narendra Ahuja
Narendra Ahuja University of Illinois at Urbana-Champaign
Ravishankar K. Iyer
Ravishankar K. Iyer University of Illinois at Urbana-Champaign
Wu-Tung Cheng
Wu-Tung Cheng Mentor Graphics
Pinaki Mazumder
Pinaki Mazumder University of Michigan–Ann Arbor

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