2005 - Fellow of the American Association for the Advancement of Science (AAAS)
2000 - ACM Fellow For contributions in parallel computing, specifically in the design of parallel algorithms for VLSI CAD, and the development of parallelizing compiler techniques for distributed memory multiprocessors.
1995 - IEEE Fellow For contributions to the application of parallel computing to computer-aided design of VLSI circuits.
His primary scientific interests are in Parallel computing, Compiler, Very-large-scale integration, Parallel algorithm and Distributed memory. His Parallel computing research is multidisciplinary, incorporating perspectives in Simulated annealing, Algorithm, Distributed computing, Fortran and Data structure. His studies in Compiler integrate themes in fields like Computer architecture, Auxiliary memory, Parallelism, Scheme and Computation.
His Very-large-scale integration research includes elements of CMOS, Algebra, Logic level and Fault detection and isolation. His Parallel algorithm research is multidisciplinary, relying on both Multiprocessing, Automatic test pattern generation, Fault coverage and Parallel processing. His research in Distributed memory intersects with topics in Message passing, Data parallelism, Intel Paragon and Programmer.
His primary areas of investigation include Parallel computing, Parallel algorithm, Algorithm, Compiler and Distributed memory. Parallel computing is closely attributed to Very-large-scale integration in his research. His study on Parallel algorithm also encompasses disciplines like
His Algorithm research focuses on Fault tolerance and how it connects with Reliability. The study incorporates disciplines such as Computer architecture, MATLAB, Programming paradigm and Fortran in addition to Compiler. As part of one scientific family, Prithviraj Banerjee deals mainly with the area of Distributed memory, narrowing it down to issues related to the Data parallelism, and often Instruction-level parallelism.
The scientist’s investigation covers issues in Parallel computing, Compiler, Field-programmable gate array, Algorithm and Computer architecture. His Parallel computing study frequently links to related topics such as Fortran. The Compiler study combines topics in areas such as SPMD, MATLAB and Linear algebra.
His Field-programmable gate array research focuses on subjects like Digital signal processing, which are linked to Hardware design languages. His work on Iterative method as part of his general Algorithm study is frequently connected to Relaxation, thereby bridging the divide between different branches of science. His Parallel algorithm study combines topics from a wide range of disciplines, such as Scalability and Very-large-scale integration.
Prithviraj Banerjee spends much of his time researching Compiler, Parallel computing, Field-programmable gate array, MATLAB and Algorithm. Compiler is a subfield of Programming language that he tackles. His study in the field of Distributed memory and Parallel processing also crosses realms of Fast multipole method.
His work in Field-programmable gate array addresses subjects such as Floating point, which are connected to disciplines such as Auxiliary memory, Integer, Hardware register, Computational science and Lookup table. He has researched MATLAB in several fields, including Control flow, Inference engine, Register allocation and Benchmark. While the research belongs to areas of Algorithm, Prithviraj Banerjee spends his time largely on the problem of Transformation matrix, intersecting his research to questions surrounding Parallelism, Program optimization, Loop fission and Locality of reference.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Zhi Alex Ye;Andreas Moshovos;Scott Hauck;Prithviraj Banerjee.
international symposium on computer architecture (2000)
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Zhi Alex Ye;Andreas Moshovos;Scott Hauck;Prithviraj Banerjee.
international symposium on computer architecture (2000)
Demonstration of automatic data partitioning techniques for parallelizing compilers on multicomputers
M. Gupta;P. Banerjee.
IEEE Transactions on Parallel and Distributed Systems (1992)
Demonstration of automatic data partitioning techniques for parallelizing compilers on multicomputers
M. Gupta;P. Banerjee.
IEEE Transactions on Parallel and Distributed Systems (1992)
The Paradigm compiler for distributed-memory multicomputers
P. Banerjee;J.A. Chandy;M. Gupta;Iv. E.W. Hodges.
IEEE Computer (1995)
The Paradigm compiler for distributed-memory multicomputers
P. Banerjee;J.A. Chandy;M. Gupta;Iv. E.W. Hodges.
IEEE Computer (1995)
Algorithm-based fault detection for signal processing applications
A.L.N. Reddy;P. Banerjee.
IEEE Transactions on Computers (1990)
Algorithm-based fault detection for signal processing applications
A.L.N. Reddy;P. Banerjee.
IEEE Transactions on Computers (1990)
An evaluation of multiple-disk I/O systems
A.L.N. Reddy;P. Banerjee.
IEEE Transactions on Computers (1989)
An evaluation of multiple-disk I/O systems
A.L.N. Reddy;P. Banerjee.
IEEE Transactions on Computers (1989)
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