2016 - ACM Fellow For contributions to the enhancement of performance and reliability in integrated circuits.
2003 - IEEE Fellow For contributions to the optimization of timing and layout in VLSI circuits.
His primary areas of study are Electronic engineering, Integrated circuit design, Algorithm, Electronic circuit and Transistor. His study of Physical design is a part of Electronic engineering. The various areas that he examines in his Integrated circuit design study include Spice, Very-large-scale integration, Worst-case complexity and Three-dimensional integrated circuit.
His Algorithm study incorporates themes from Standard deviation, Monte Carlo method, Statistical static timing analysis and Timing failure. His Electronic circuit research incorporates elements of Subthreshold conduction, CMOS, Logic gate and Capacitor. His biological study spans a wide range of topics, including Mathematical optimization and Leakage.
Electronic engineering, Electronic circuit, Algorithm, Integrated circuit design and Very-large-scale integration are his primary areas of study. Sachin S. Sapatnekar studied Electronic engineering and Transistor that intersect with Leakage. His Electronic circuit study integrates concerns from other disciplines, such as CMOS, Static timing analysis and Benchmark.
As part of his studies on Algorithm, he often connects relevant areas like Monte Carlo method. His work in Integrated circuit design tackles topics such as Physical design which are related to areas like Floorplan. His research investigates the connection between Very-large-scale integration and topics such as Integrated circuit layout that intersect with issues in Routing.
Sachin S. Sapatnekar focuses on Electronic engineering, Electronic circuit, Computer engineering, Logic gate and Algorithm. His Electronic engineering study incorporates themes from Threshold voltage, Pass transistor logic, Transistor, Electromigration and Redundancy. His study in Electronic circuit is interdisciplinary in nature, drawing from both Netlist, Graph, Ring oscillator and Benchmark.
His Computer engineering research includes elements of Discrete cosine transform, Artificial neural network, Integrated circuit design, Adder and Implementation. Sachin S. Sapatnekar has researched Logic gate in several fields, including AND gate, Overhead and Inverter. His Algorithm research is multidisciplinary, incorporating perspectives in Power network design and Circuit design.
Sachin S. Sapatnekar mainly investigates Computer engineering, Electronic engineering, Electronic circuit, Spintronics and Logic gate. The concepts of his Computer engineering study are interwoven with issues in Graph, Discrete cosine transform, Integrated circuit design, Artificial neural network and Convolutional neural network. Electronic engineering is frequently linked to Electromigration in his study.
His work carried out in the field of Electronic circuit brings together such families of science as Ring oscillator and Benchmark. His research in Spintronics tackles topics such as Electrical engineering which are related to areas like Energy and Energy harvesting. His Logic gate study combines topics in areas such as Magnetoresistive random-access memory, Overhead, CMOS and Inverter.
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Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Hongliang Chang;Sachin S. Sapatnekar.
international conference on computer aided design (2003)
Hierarchical analysis of power distribution networks
M. Zhao;R.V. Panda;S.S. Sapatnekar;D. Blaauw.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2002)
Thermal via placement in 3D ICs
Brent Goplen;Sachin Sapatnekar.
international symposium on physical design (2005)
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization
S.S. Sapatnekar;V.B. Rao;P.M. Vaidya;Sung-Mo Kang.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1993)
Impact of NBTI on SRAM Read Stability and Design for Reliability
Sanjay V. Kumar;Chris H. Kim;Sachin S. Sapatnekar.
international symposium on quality electronic design (2006)
Statistical timing analysis under spatial correlations
Hongliang Chang;S.S. Sapatnekar.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2005)
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Brent Goplen;Sachin Sapatnekar.
international conference on computer aided design (2003)
A practical methodology for early buffer and wire resource allocation
C.J. Alpert;Jiang Hu;S.S. Sapatnekar;P.G. Villarrubia.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2003)
Full-chip analysis of leakage power under process variations, including spatial correlations
Hongliang Chang;Sachin S. Sapatnekar.
design automation conference (2005)
Handbook of Algorithms for Physical Design Automation
Charles J. Alpert;Dinesh P. Mehta;Sachin S. Sapatnekar.
(2008)
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