2026 Sachin S. Sapatnekar: Electronics and Electrical Engineering Researcher – H-Index, Publications & Awards

Discipline name	D-Index	World Ranking	Current World Ranking	National Ranking	Current National Ranking	Publications	Citations
Computer Science	68	2095	2030	1057	1017	515	17880
Electronics and Electrical Engineering	68	1017	970	430	395	517	17947

Research.com Recognitions

2016 - ACM Fellow For contributions to the enhancement of performance and reliability in integrated circuits.
2003 - IEEE Fellow For contributions to the optimization of timing and layout in VLSI circuits.

Overview

Sachin S. Sapatnekar is affiliated with the University of Minnesota in the United States. Their research spans the fields of Engineering and Computer Science, with a focus on Electrical and Electronic Engineering, Artificial Intelligence, Hardware and Architecture, Computer Vision and Pattern Recognition, and Computer Networks and Communications.

The main topics of their work include:

VLSI and FPGA Design Techniques
Advanced Memory and Neural Computing
Ferroelectric and Negative Capacitance Devices
Low-power high-performance VLSI design
VLSI and Analog Circuit Testing
Quantum Computing Algorithms and Architecture
Semiconductor materials and devices

Frequent co-authors collaborating with Sachin S. Sapatnekar are:

Ulya R. Karpuzcu
Ramesh Harjani
Hüsrev Cılasun
Meghna Madhusudan
Vidya A. Chhabria

Their contributions have been published across a variety of venues, most notably:

arXiv (Cornell University)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Transactions on Design Automation of Electronic Systems
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

Recent papers authored by Sachin S. Sapatnekar include:

"A 1,968-node coupled ring oscillator circuit for combinatorial optimization problem solving" (2022, Nature Electronics)
"An Ising solver chip based on coupled ring oscillators with a 48-node all-to-all connected array architecture" (2023, Nature Electronics)
"Analytical Modeling of Transient Electromigration Stress based on Boundary Reflections" (2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD))
"BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology" (2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD))
"A DNA Read Alignment Accelerator Based on Computational RAM" (2020, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits)

Sachin S. Sapatnekar has received professional recognition including the ACM Fellow award in 2016 for contributions to the enhancement of performance and reliability in integrated circuits. Earlier, in 2003, they were named an IEEE Fellow for contributions to the optimization of timing and layout in VLSI circuits.

Best Publications

Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal

Hongliang Chang;Sachin S. Sapatnekar

709
Citations
Hierarchical analysis of power distribution networks

M. Zhao;R.V. Panda;S.S. Sapatnekar;D. Blaauw

452
Citations
Thermal via placement in 3D ICs

Brent Goplen;Sachin Sapatnekar

407
Citations
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization

S.S. Sapatnekar;V.B. Rao;P.M. Vaidya;Sung-Mo Kang

392
Citations
Impact of NBTI on SRAM Read Stability and Design for Reliability

Sanjay V. Kumar;Chris H. Kim;Sachin S. Sapatnekar

392
Citations
Handbook of Algorithms for Physical Design Automation

Charles J. Alpert;Dinesh P. Mehta;Sachin S. Sapatnekar

355
Citations
Statistical timing analysis under spatial correlations

Hongliang Chang;S.S. Sapatnekar

353
Citations
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach

Brent Goplen;Sachin Sapatnekar

343
Citations
A practical methodology for early buffer and wire resource allocation

C.J. Alpert;Jiang Hu;S.S. Sapatnekar;P.G. Villarrubia

326
Citations
Full-chip analysis of leakage power under process variations, including spatial correlations

Hongliang Chang;Sachin S. Sapatnekar

300
Citations
NBTI-aware synthesis of digital circuits

Sanjay V. Kumar;Chris H. Kim;Sachin S. Sapatnekar

289
Citations
An analytical model for negative bias temperature instability

Sanjay V. Kumar;Chris H. Kim;Sachin S. Sapatnekar

277
Citations
A graph-theoretic approach to clock skew optimization

R.B. Deokar;S.S. Sapatnekar

228
Citations
Placement and routing in 3D integrated circuits

C. Ababei;Y. Feng;B. Goplen;Hushrav Mogal

225
Citations
Random walks in a supply network

Haifeng Qian;Sani R. Nassif;Sachin S. Sapatnekar

221
Citations
Power grid analysis using random walks

Haifeng Qian;S.R. Nassif;S.S. Sapatnekar

219
Citations
Placement of thermal vias in 3-D ICs using various thermal objectives

B. Goplen;S.S. Sapatnekar

193
Citations
Three Dimensional Integrated Circuit Design

Yuan Xie;Jason Cong;Sachin Sapatnekar

187
Citations
Hierarchical analysis of power distribution networks

Min Zhao;Rajendran V. Panda;Sachin S. Sapatnekar;Tim Edwards

179
Citations
Proceedings - Design Automation Conference

Vidyasagar Nookala;Sachin S Sapatnekar

62
Citations
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Yong Zhan;Yan Feng;Sachin S Sapatnekar

30
Citations
Clock Skew Optimization

Naresh Maheshwari;Sachin S. Sapatnekar

1
Citations

Frequent Co-Authors

Jiang Hu Texas A&M University

Chris H. Kim University of Minnesota

Jian-Ping Wang University of Minnesota

David J. Lilja University of Minnesota

Charles J. Alpert Cadence Design Systems

Jordi Cortadella Universitat Politècnica de Catalunya

Ramesh Harjani University of Minnesota

Sung-Mo Kang University of California, Santa Cruz

Keshab K. Parhi University of Minnesota

David Blaauw University of Michigan–Ann Arbor

External Links

Personal website of Sachin S. Sapatnekar Google Scholar page

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