World's Best Scientists 2026 revealed!

D-Index & Metrics

Computer Science

D-Index
48
Citations
10453
World Ranking
6131
National Ranking
2757

Electronics and Electrical Engineering

D-Index
47
Citations
9936
World Ranking
3190
National Ranking
1192

Overview

Chung-Kuan Cheng is affiliated with the University of California, San Diego in the United States. Their research spans primarily Engineering and Computer Science, with a focus on Electrical and Electronic Engineering, Hardware and Architecture, Computer Networks and Communications, Biomedical Engineering, and Artificial Intelligence.

Their work covers a variety of topics including:

  • VLSI and FPGA Design Techniques
  • VLSI and Analog Circuit Testing
  • Interconnection Networks and Systems
  • Advancements in Semiconductor Devices and Circuit Design
  • Low-power high-performance VLSI design
  • Traumatic Brain Injury Research
  • Semiconductor materials and devices

Recent publications by Chung-Kuan Cheng include:

  • Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Chung-Kuan Cheng has co-authored papers with several researchers, including:

  • Bill Lin
  • Daeyeal Lee
  • Chester Holtz
  • Chia-Tung Ho
  • Dongwon Park

They have frequently published in venues such as:

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • arXiv (Cornell University)
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
  • Advanced Sensor Research

Best Publications

  • Optimal wire sizing and buffer insertion for low power and a generalized delay model

    J. Lillis;Chung-Kuan Cheng;T.-T.Y. Lin

  • An O-tree representation of non-slicing floorplan and its applications

    Pei-Ning Guo;Chung-Kuan Cheng;Takeshi Yoshimura

  • Corner block list: an effective and efficient topological representation of non-slicing floorplan

    Xianlong Hong;Gang Huang;Yici Cai;Jiangchun Gu

  • Interconnect analysis and synthesis

    Chung-Kuan Cheng

  • Ratio cut partitioning for hierarchical designs

    Y.-C. Wei;C.-K. Cheng

  • Towards efficient hierarchical designs by ratio cut partitioning

    Yen-Chuen Wei;Chung-Kuan Cheng

  • Module Placement Based on Resistive Network Optimization

    Chung-Kuan Cheng;E.S. Kuh

  • An improved two-way partitioning algorithm with stable performance (VLSI)

    C.-K. Cheng;Y.-C.A. Wei

  • A general purpose, multiple-way partitioning algorithm

    Ching-Wei Yeh;Chung-Kuan Cheng;T.T.Y. Lin

  • RePlAce: Advancing Solution Quality and Routability Validation in Global Placement

    Chung-Kuan Cheng;Andrew B. Kahng;Ilgweon Kang;Lutong Wang

  • New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

    John Lillis;Chung-Kuan Cheng;Ting-Ting Y. Lin;Ching-Yen Ho

  • Floorplanning using a tree representation

    Pei-Ning Guo;T. Takahashi;Chung-Kuan Cheng;T. Yoshimura

  • ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method

    Jingwei Lu;Pengwen Chen;Chin-Chih Chang;Lu Sha

  • Performance-Driven Steiner Tree Algorithms for Global Routing

    Xianlong Hong;Tianxiong Xue;Ernest S. Kuh;Chung-Kuan Cheng

  • Area minimization of power distribution network using efficient nonlinear programming techniques

    Xiaohai Wu;Xianlong Hong;Yici Cai;C. K. Cheng

  • Physical planning of on-chip interconnect architectures

    Hongyu Chen;Bo Yao;Feng Zhou;Chung-Kuan Cheng

  • MUTUAL CONNECTION DELAY DRIVE TYPE PLACEMENT AND ROUTING FOR DESIGNING INTEGRATED CIRCUIT

    Cheng C K;Yao So-Zen

  • Area minimization of power distribution network using efficient nonlinear programming techniques

    Xiaohai Wu;Xianlong Hong;Yici Cai;Zuying Luo

  • ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits

    Jingwei Lu;Hao Zhuang;Pengwen Chen;Hongliang Chang

  • An enhanced perturbing algorithm for floorplan design using the O-tree representation

    Yingxin Pang;Chung-Kuan Cheng;Takeshi Yoshimura

  • Floorplan representations: Complexity and connections

    Bo Yao;Hongyu Chen;Chung-Kuan Cheng;Ronald Graham

Frequent Co-Authors

Ernest S. Kuh
Ernest S. Kuh University of California, Berkeley
Ron Graham
Ron Graham University of California, San Diego
James F. Buckwalter
James F. Buckwalter University of California, Santa Barbara
Andrew B. Kahng
Andrew B. Kahng University of California, San Diego
Tzyy-Ping Jung
Tzyy-Ping Jung University of California, San Diego
Yijun Wang
Yijun Wang Chinese Academy of Sciences
Evangeline F. Y. Young
Evangeline F. Y. Young Chinese University of Hong Kong
Sing H. Lee
Sing H. Lee University of California, San Diego
Patrick P. Mercier
Patrick P. Mercier University of California, San Diego
Bill Lin
Bill Lin University of California, San Diego

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