2026 Cheng-Kok Koh: Electronics and Electrical Engineering Researcher – H-Index, Publications & Awards

Discipline name	D-Index	World Ranking	Current World Ranking	National Ranking	Current National Ranking	Publications	Citations
Electronics and Electrical Engineering	36	5358	5144	1852	1728	190	5219

Overview

Cheng-Kok Koh is affiliated with Purdue University West Lafayette in the United States. Their research spans multiple fields including Computer Science and Engineering, with a focus on subfields such as Electrical and Electronic Engineering, Computer Networks and Communications, Hardware and Architecture, Computational Mechanics, and Information Systems.

The scientist's work addresses several main topics, including:

VLSI and FPGA Design Techniques
Interconnection Networks and Systems
Embedded Systems Design Techniques
Real-Time Systems Scheduling
Low-power high-performance VLSI design
Cloud Computing and Resource Management
Distributed and Parallel Computing Systems

Cheng-Kok Koh has authored research published primarily in the following venues:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
arXiv (Cornell University)
IEEE Transactions on Components Packaging and Manufacturing Technology

Recent papers authored or co-authored by Cheng-Kok Koh include:

"A Scalable Buffer Queue Sizing Algorithm for Latency Insensitive Systems," 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
"A Scalable, Memory-Efficient Algorithm for Minimum Cycle Mean Calculation in Directed Graphs," 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
"Saath: Speeding up CoFlows by Exploiting the Spatial Dimension," 2021, arXiv (Cornell University)
"Real-Time 3-D Thermal Simulation of Advanced Packages via Generative Adversarial Networks," 2024, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
"Multiphysics-Informed ML-Assisted Chiplet Floorplanning for Heterogeneous Integration," 2025, IEEE Transactions on Components Packaging and Manufacturing Technology

The scientist frequently collaborates with several co-authors including Supriyo Maji, Seunghyun Hwang, Vinicius C. do Nascimento, Qiang Qiu, and Ganesh Subbarayan. These collaborations are reflected in multiple publications across the venues noted above.

Best Publications

Performance optimization of VLSI interconnect layout

Jason Cong;Lei He;Cheng-Kok Koh;Patrick H. Madden

424
Citations
Interconnect design for deep submicron ICs

Jason Cong;Zhigang Pan;Lei He;Cheng-Kok Koh

271
Citations
Routability-Driven Placement and White Space Allocation

Chen Li;Min Xie;Cheng-Kok Koh;J. Cong

268
Citations
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning

Shiyou Zhao;K. Roy;Cheng-Kok Koh

237
Citations
Bounded-skew clock and Steiner routing

Jason Cong;Andrew B. Kahng;Cheng-Kok Koh;C.-W. Albert Tsao

195
Citations
Simultaneous driver and wire sizing for performance and power optimization

J. Cong;Cheng-Kok Koh

174
Citations
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures

Cheng-Kok Koh;Patrick H. Madden

147
Citations
Recursive bisection based mixed block placement

Ateen Khatkhate;Chen Li;Ameya R. Agnihotri;Mehmet C. Yildiz

125
Citations
UST/DME: a clock tree router for general skew constraints

Chung-wen Albert Tsao;Cheng-kok Koh

118
Citations
Routability-driven repeater block planning for interconnect-centric floorplanning

P. Sarkar;V. Sundararaman;C.-K. Koh

116
Citations
Simultaneous buffer and wire sizing for performance and power optimization

J. Cong;Cheng-Kok Koh;Kwok-Shing Leung

100
Citations
Minimum-cost bounded-skew clock routing

J. Cong;Cheng-Kok Koh

96
Citations
Flip-Flop and Repeater Insertion for Early Interconnect Planning

Ruibing Lu;Guoan Zhong;Cheng-Kok Koh;Kai-Yuan Chao

93
Citations
Processor caches built using multi-level spin-transfer torque RAM cells

Yiran Chen;Weng-Fai Wong;Hai (Helen) Li;Cheng-Kok Koh

92
Citations
Simultaneous buffer and wire sizing for performance and power optimization

Unknown

87
Citations
Decoupling capacitance allocation for power supply noise suppression

Shiyou Zhao;Kaushik Roy;Cheng-Kok Koh

84
Citations
Power supply noise suppression via clock skew scheduling

W.-C.D. Lam;Cheng-Kok Koh;C.-W.A. Tsao

83
Citations
A twisted-bundle layout structure for minimizing inductive coupling noise

Guoan Zhong;Cheng Kok Koh;Kaushik Roy

77
Citations
Global interconnect sizing and spacing with consideration of coupling capacitance

Jason Cong;Lei He;Cheng-Kok Koh;Zhigang Pan

77
Citations
Exact closed-form formula for partial mutual inductances of rectangular conductors

Guoan Zhong;Cheng-Kok Koh

72
Citations
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels

Ruibing Lu;Cheng-Kok Koh

69
Citations
Estimation of inductive and resistive switching noise on power supply network in deep sub-micron CMOS circuits

S. Zhao;K. Roy;C.-K. Koh

68
Citations
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips

Ruibing Lu;Aiqun Cao;Cheng-Kok Koh

65
Citations

Frequent Co-Authors

Kaushik Roy Purdue University West Lafayette

Hai Li Duke University

David B. Janes Purdue University West Lafayette

Lei He University of California, Los Angeles

Jiang Hu Texas A&M University

Gerhard Klimeck Purdue University West Lafayette

Andrew B. Kahng University of California, San Diego

Tung-Sang Ng University of Hong Kong

Dinesh Somasekhar Intel (United States)

William J. Chappell Purdue University West Lafayette

External Links

Personal website of Cheng-Kok Koh

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