2011 - ACM Distinguished Member
2006 - Fellow of Alfred P. Sloan Foundation
Li-Shiuan Peh focuses on Computer network, Interconnection, Network on a chip, Router and Embedded system. His research in the fields of Flow control, Network planning and design, Latency and Broadcast communication network overlaps with other disciplines such as Cache coherence. His Interconnection research is multidisciplinary, relying on both Dynamic demand, Power optimization, Energy consumption, Simulation and Key.
His Network on a chip research incorporates themes from Network architecture, Design space exploration, System on a chip and Electronic engineering, Bandwidth. His System on a chip study combines topics from a wide range of disciplines, such as Telecommunications, Computer architecture and Microarchitecture. His Embedded system research integrates issues from Scalability, Software, Multi-core processor and Packet switching.
His primary scientific interests are in Computer network, Embedded system, Network on a chip, Interconnection and Scalability. His Computer network study frequently draws connections between adjacent fields such as Throughput. He combines subjects such as Compiler, Dynamic voltage scaling, Chip, Software and Multi-core processor with his study of Embedded system.
His Network on a chip research is multidisciplinary, incorporating elements of Network architecture, Design space exploration, Microarchitecture, Network topology and System on a chip. His research in System on a chip intersects with topics in Routing, Computer architecture and Crossbar switch. His work deals with themes such as Network performance, Power optimization, Energy consumption, Low-power electronics and Packet switching, which intersect with Interconnection.
His scientific interests lie mostly in Embedded system, Computer network, Electrical engineering, Network packet and Wearable computer. His research integrates issues of Baseband, Compiler and Electrical efficiency in his study of Embedded system. When carried out as part of a general Computer network research project, his work on Network architecture is frequently linked to work in Mobile Web, therefore connecting diverse disciplines of study.
The Network packet study combines topics in areas such as Chip, Router, Network detector, Service discovery and Mobile device. He has included themes like Scalability, Deflection routing, Mesh networking and Routing protocol in his Router study. His Wearable technology study integrates concerns from other disciplines, such as ARM architecture, Power budget and Network on a chip.
The scientist’s investigation covers issues in Optoelectronics, High-electron-mobility transistor, Single cycle, Computer network and Router. His Optoelectronics study incorporates themes from Speech recognition, Optical interconnect and Die. His studies in High-electron-mobility transistor integrate themes in fields like Radio frequency, Transmitter, Multiplexing, Electronic engineering and Noise figure.
His work in Single cycle incorporates the disciplines of Routing protocol, Bandwidth throttling, Scalability, Compiler and Embedded system. The various areas that Li-Shiuan Peh examines in his Computer network study include Chip and Mesh networking. His Router study combines topics in areas such as Deflection routing and Power usage.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Energy-efficient computing for wildlife tracking: design tradeoffs and early experiences with ZebraNet
architectural support for programming languages and operating systems (2002)
Orion: a power-performance simulator for interconnection networks
Hang-Sheng Wang;Xinping Zhu;Li-Shiuan Peh;Sharad Malik.
international symposium on microarchitecture (2002)
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Andrew B. Kahng;Bin Li;Li-Shiuan Peh;Kambiz Samadi.
design, automation, and test in europe (2009)
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
R. Marculescu;U.Y. Ogras;Li-Shiuan Peh;N.E. Jerger.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2009)
GARNET: A detailed on-chip network model inside a full-system simulator
Niket Agarwal;Tushar Krishna;Li-Shiuan Peh;Niraj K. Jha.
international symposium on performance analysis of systems and software (2009)
A delay model and speculative architecture for pipelined routers
L.-S. Peh;W.J. Dally.
high performance computer architecture (2001)
Research Challenges for On-Chip Interconnection Networks
J.D. Owens;W.J. Dally;R. Ho;D.N. Jayasimha.
IEEE Micro (2007)
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
Chen Sun;Chia-Hsin Owen Chen;George Kurian;Lan Wei.
networks on chips (2012)
Dynamic voltage scaling with links for power optimization of interconnection networks
Li Shang;Li-Shiuan Peh;N.K. Jha.
high-performance computer architecture (2003)
Express virtual channels: towards the ideal interconnection fabric
Amit Kumar;Li-Shiuan Peh;Partha Kundu;Niraj K. Jha.
international symposium on computer architecture (2007)
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