Axel Jantsch mostly deals with Network on a chip, Embedded system, Computer network, System on a chip and Computer architecture. Axel Jantsch has researched Network on a chip in several fields, including Network architecture, Network packet, Fault tolerance, Network topology and Real-time computing. His Embedded system research includes elements of Logic synthesis, Model of computation, Systems design, Software and Multi-core processor.
His Multi-core processor study integrates concerns from other disciplines, such as Resource allocation, Platform-based design, Data link layer, Physical layer and Memory bank. His System on a chip study incorporates themes from Tree and SDET. His studies deal with areas such as Integrated circuit design, Multiprocessing, Benchmark, Hardware architecture and Testability as well as Computer architecture.
Embedded system, Network on a chip, Distributed computing, Computer network and Computer architecture are his primary areas of study. The concepts of his Embedded system study are interwoven with issues in Software and Multi-core processor. His Network on a chip study combines topics in areas such as Network architecture, Parallel computing, Fault tolerance, Network topology and System on a chip.
His study ties his expertise on Distributed shared memory together with the subject of Parallel computing. Network packet and Networks on chip are among the areas of Computer network where Axel Jantsch concentrates his study. His work on Network packet is being expanded to include thematically relevant topics such as Router.
His scientific interests lie mostly in Distributed computing, Reliability, Embedded system, Artificial intelligence and Dark silicon. His research in Distributed computing intersects with topics in Automation, Scalability, Quality of service, Dynamic priority scheduling and Robustness. His Quality of service research is multidisciplinary, incorporating elements of Mixed criticality and System on a chip.
His Embedded system research is multidisciplinary, relying on both Trojan, Network packet and Router. His work on Network on a chip expands to the thematically related Network packet. His study in Dark silicon is interdisciplinary in nature, drawing from both Frequency scaling and Chip.
His primary scientific interests are in Artificial intelligence, Dark silicon, Reliability, Embedded system and Power budget. His research on Artificial intelligence also deals with topics like
His research integrates issues of Taxonomy, Software, Network packet and Router in his study of Embedded system. The various areas that Axel Jantsch examines in his Network packet study include Code coverage, Interface and Fault detection and isolation. As a part of the same scientific family, he mostly works in the field of Router, focusing on Blocking and, on occasion, Network on a chip and Chip.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Networks on chip
Axel Jantsch;Hannu Tenhunen.
IEEE Computer (2003)
A network on chip architecture and design methodology
S. Kumar;A. Jantsch;J.-P. Soininen;M. Forsell.
ieee computer society annual symposium on vlsi (2002)
Network on Chip : An architecture for billion transistor era
Ahmed Hemani;Axel Jantsch;Shashi Kumar;Adam Postula.
norchip (2000)
Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip
Mikael Millberg;Erland Nilsson;Rikard Thid;Axel Jantsch.
design, automation, and test in europe (2004)
The Nostrum backbone-a communication protocol stack for Networks on Chip
M. Millberg;E. Nilsson;R. Thid;S. Kumar.
international conference on vlsi design (2004)
Methods for fault tolerance in networks-on-chip
Martin Radetzki;Chaochao Feng;Xueqian Zhao;Axel Jantsch.
ACM Computing Surveys (2013)
System modeling and transformational design refinement in ForSyDe [formal system design]
I. Sander;A. Jantsch.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2004)
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
Erland Nilsson;Mikael Millberg;Johnny Oberg;Axel Jantsch.
design, automation, and test in europe (2003)
Run-time Partial Reconfiguration speed investigation and architectural design space exploration
Ming Liu;Wolfgang Kuehn;Zhonghai Lu;Axel Jantsch.
field-programmable logic and applications (2009)
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
Heiko Zimmer;Axel Jantsch.
international conference on hardware/software codesign and system synthesis (2003)
Profile was last updated on December 6th, 2021.
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