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Davide Bertozzi

Davide Bertozzi

D-Index & Metrics

Engineering and Technology

D-Index
33
Citations
6642
World Ranking
9337
National Ranking
370

Overview

Davide Bertozzi is affiliated with the University of Ferrara in Italy and has contributed extensively in the fields of Engineering and Computer Science, with a particular focus on Electrical and Electronic Engineering. Their research spans key subfields including Artificial Intelligence, Computer Networks and Communications, Cellular and Molecular Neuroscience, as well as Atomic and Molecular Physics, and Optics.

Their work addresses several main topics such as Advanced Memory and Neural Computing, Photonic and Optical Devices, and Optical Network Technologies. Other notable research interests include Ferroelectric and Negative Capacitance Devices, Advanced Photonic Communication Systems, Advanced Optical Network Technologies, and Interconnection Networks and Systems.

Frequent coauthors in their research include Giovanna Calò, Gaetano Bellanca, Marina Barbiroli, Franco Fuschini, and Velio Tralli. Bertozzi's contributions have been published in various venues, including Optics Express, IEEE Journal of Quantum Electronics, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Photonics, and IEEE Journal on Selected Areas in Communications.

Their recent papers include:

  • "Design of reconfigurable on-chip wireless interconnections through Optical Phased Arrays," 2021, Optics Express
  • "PSION+: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs," 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • "Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems," 2020, IEEE Micro
  • "Reconfigurable Optical Wireless Switches for On-Chip Interconnection," 2022, IEEE Journal of Quantum Electronics
  • "An Ultra-Low Cost and Multicast-Enabled Asynchronous NoC for Neuromorphic Edge Computing," 2024, IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Best Publications

  • NoC synthesis flow for customized domain specific multiprocessor systems-on-chip

    D. Bertozzi;A. Jalabert;Srinivasan Murali;R. Tamhankar

  • Xpipes: a network-on-chip architecture for gigascale systems-on-chip

    D. Bertozzi;L. Benini

  • MPARM: Exploring the Multi-Processor SoC Design Space with SystemC

    Luca Benini;Davide Bertozzi;Alessandro Bogliolo;Francesco Menichelli

  • Error control schemes for on-chip communication links: the energy-reliability tradeoff

    D. Bertozzi;L. Benini;G. De Micheli

  • Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs

    Matteo Dall'Osso;Gianluca Biccari;Luca Giovannini;Davide Bertozzi

  • Analyzing on-chip communication in a MPSoC environment

    Mirko Loghi;Federico Angiolini;Davide Bertozzi;Luca Benini

  • Supporting Task Migration in Multi-Processor Systems-on-Chip: A Feasibility Study

    S. Bertozzi;A. Acquaviva;D. Bertozzi;A. Poggiali

  • Network-on-chip architectures and design methods

    Luca Benini;Davide Bertozzi

  • Low Power Error Resilient Encoding for On-Chip Data Buses

    D. Bertozzi;L. Benini;G. de Micheli

  • /spl times/pipes Lite: a synthesis oriented design library for networks on chips

    S. Stergiou;F. Angiolini;S. Carta;L. Raffo

  • SystemC cosimulation and emulation of multiprocessor SoC designs

    L. Benini;D. Bertozzi;D. Bruni;N. Drago

  • A high-efficiency wind-flow energy harvester using micro turbine

    Davide Carli;Davide Brunelli;Davide Bertozzi;Luca Benini

  • Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip

    M. Ruggiero;A. Guerri;D. Bertozzi;F. Poletti

  • Fault tolerance overhead in network-on-chip flow control schemes

    Antonio Pullini;Federico Angiolini;Davide Bertozzi;Luca Benini

  • Efficient implementation of distributed routing algorithms for NoCs

    Samuel Rodrigo;Simone Medardoni;José Flich;Davide Bertozzi

  • Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing

    S. Rodrigo;J. Flich;A. Roca;S. Medardoni

  • Designing Network On-Chip Architectures in the Nanoscale Era

    Jose Flich;Davide Bertozzi

  • Performance Analysis of Arbitration Policies for SoC Communication Architectures

    Francesco Poletti;Davide Bertozzi;Luca Benini;Alessandro Bogliolo

  • Allocation and scheduling for MPSoCs via decomposition and no-good generation

    Luca Benini;Davide Bertozzi;Alessio Guerri;Michela Milano

  • Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints

    D. Ludovici;F. Gilabert;S. Medardoni;C. Gómez

  • Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs

    Unknown

Frequent Co-Authors

Luca Benini
Luca Benini ETH Zurich
Michela Milano
Michela Milano University of Bologna
Giovanni Capranico
Giovanni Capranico University of Bologna
G. De Micheli
G. De Micheli École Polytechnique Fédérale de Lausanne
Pedro López
Pedro López Universitat Politècnica de València
Bruno Ricco
Bruno Ricco University of Bologna
José Duato
José Duato Universitat Politècnica de València
Jose Flich
Jose Flich Universitat Politècnica de València
Massimo Poncino
Massimo Poncino Polytechnic University of Turin

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