2026 Fernando Moraes: Computer Science Researcher – H-Index, Publications & Awards

Overview

Fernando Moraes is affiliated with the Pontifical Catholic University of Rio Grande do Sul in Brazil. Their research primarily spans the fields of Computer Science and Engineering, with substantial contributions in Electrical and Electronic Engineering, Computer Networks and Communications, Hardware and Architecture, Computer Vision and Pattern Recognition, and Artificial Intelligence.

The scientist's work engages deeply with a range of specialized topics, including Advanced Memory and Neural Computing, Interconnection Networks and Systems, Parallel Computing and Optimization Techniques, Radiation Effects in Electronics, Embedded Systems Design Techniques, Software-Defined Networks and 5G, and Advanced Neural Network Applications.

Fernando Moraes has authored multiple papers published in a variety of scientific venues. Recent publications include:

A Systemic and Secure SDN Framework for NoC-Based Many-Cores (2020, IEEE Access)
A New Router Architecture for High-Performance Intrachip Networks (2020, Journal of Integrated Circuits and Systems)
Evaluation of the soft error assessment consistency of a JIT-based virtual platform simulator (2021, IET Computers & Digital Techniques)
Buffer Sizing for Multimedia Flows in Packet-Switching NoCs (2020, Journal of Integrated Circuits and Systems)
A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators (2021, IEEE Transactions on Circuits and Systems I Regular Papers)

Their frequent collaborative partners include Luciano Lores Caimi, Ney Calazans, Ricardo Reis, Leonardo Rezende Juracy, and Marcelo Ruaro.

Fernando Moraes's papers have appeared mainly in the following publication venues:

Journal of Integrated Circuits and Systems
IEEE Access
IEEE Design and Test
Analog Integrated Circuits and Signal Processing
IEEE Transactions on Nuclear Science

Best Publications

HERMES: an infrastructure for low area overhead packet-switching networks on chip

Fernando Moraes;Ney Calazans;Aline Mello;Leandro Möller

808
Citations
Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs

E. Carvalho;N. Calazans;F. Moraes

210
Citations
Dynamic Task Mapping for MPSoCs

Ewerson Luiz de Souza Carvalho;Ney Laert Vilar Calazans;Fernando Gehm Moraes

194
Citations
Virtual channels in networks on chip: implementation and evaluation on hermes NoC

Aline Mello;Leonel Tedesco;Ney Calazans;Fernando Moraes

170
Citations
A scalable test strategy for network-on-chip routers

A.M. Amory;E. Briao;E. Cota;M. Lubaszewski

156
Citations
HeMPS - a framework for NoC-based MPSoC generation

Everton A. Carara;Roberto P. de Oliveira;Ney L. V. Calazans;Fernando G. Moraes

153
Citations
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique

Cesar Marcon;Ney Calazans;Fernando Moraes;Altamiro Susin

129
Citations
MAIA: a framework for networks on chip generation and verification

Luciano Ost;Aline Mello;José Palma;Fernando Moraes

104
Citations
Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses

N.L.V. Calazans;F.G. Moraes

97
Citations
Congestion-aware task mapping in heterogeneous MPSoCs

E. Carvalho;F. Moraes

96
Citations
Remote and partial reconfiguration of FPGAs: tools and trends

D. Mesquita;F. Moraes;J. Palma;L. Moller

88
Citations
Evaluation of Routing Algorithms on Mesh Based NoCs

Aline Vieira de Mello;Luciano Copello Ost;Fernando Gehm Moraes;Ney Laert Vilar Calazans

85
Citations
Comparison of network-on-chip mapping algorithms targeting low energy consumption

César Augusto Missio Marcon;Edson Ifarraguirre Moreno;Ney Laert Vilar Calazans;Fernando Gehm Moraes

82
Citations
Distributed resource management in NoC-based MPSoCs with dynamic cluster sizes

Guilherme Castilhos;Marcelo Mandelli;Guilherme Madalozzo;Fernando Moraes

71
Citations
A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping.

Fernando Gehm Moraes;Aline Mello;Leandro Möller;Luciano Ost

69
Citations
Traffic generation and performance evaluation for mesh-based NoCs

Leonel Tedesco;Aline Mello;Diego Garibotti;Ney Calazans

68
Citations
From VHDL register transfer level to SystemC transaction level modeling: a comparative case study

Ney Calazans;Edson Moreno;Fabiano Hessel;Vitor Rosa

65
Citations
NoC Power Estimation at the RTL Abstraction Level

G. Guindani;C. Reinbrecht;T. Raupp;N. Calazans

62
Citations
Core communication interface for FPGAs

José Carlos Palma;Aline Vieira de Mello;Leandro Möller;Fernando Moraes

58
Citations
Topology-agnostic fault-tolerant NoC routing method

Eduardo Wachter;Augusto Erichsen;Alexandre Amory;Fernando Moraes

58
Citations

Frequent Co-Authors

Axel Jantsch TU Wien

Erik Jan Marinissen Imec

Nikil Dutt University of California, Irvine

Kees Goossens Eindhoven University of Technology

Luigi Carro Federal University of Rio Grande do Sul

Grigory Volovik Landau Institute for Theoretical Physics

External Links

Personal website of Fernando Moraes Google Scholar page

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