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Maurizio Palesi

Maurizio Palesi

D-Index & Metrics

Computer Science

D-Index
31
Citations
4502
World Ranking
13598
National Ranking
489

Overview

Maurizio Palesi is affiliated with the University of Catania in Italy. Their research contributions focus on Computer Science and Engineering, with a significant emphasis on Electrical and Electronic Engineering, Computer Networks and Communications, Hardware and Architecture, Artificial Intelligence, and Computer Vision and Pattern Recognition.

The scientist has published extensively within the following main fields of study:

  • Computer Science
  • Engineering

Their work covers several specialized subfields, notably:

  • Electrical and Electronic Engineering
  • Computer Networks and Communications
  • Hardware and Architecture
  • Artificial Intelligence
  • Computer Vision and Pattern Recognition

Maurizio Palesi's research topics include:

  • Interconnection Networks and Systems
  • Parallel Computing and Optimization Techniques
  • Advanced Memory and Neural Computing
  • Advanced Neural Network Applications
  • Advancements in Battery Materials
  • VLSI and FPGA Design Techniques
  • Supercapacitor Materials and Fabrication

Frequent co-authors in their research collaborations are:

  • Davide Patti
  • Giuseppe Ascia
  • Vincenzo Catania
  • Enrico Russo
  • Salvatore Monteleone

Some frequently chosen publication venues for their work include:

  • arXiv (Cornell University)
  • IEEE Journal on Emerging and Selected Topics in Circuits and Systems
  • IEEE Internet of Things Journal
  • IEEE Transactions on Computers
  • TUGraz OPEN Library (Graz University of Technology)

Recent papers authored by the scientist are:

  • "An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators," 2020, IEEE Journal on Emerging and Selected Topics in Circuits and Systems
  • "A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip," 2020, TUGraz OPEN Library (Graz University of Technology)
  • "A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms," 2023, arXiv (Cornell University)
  • "DNN Model Compression for IoT Domain-Specific Hardware Accelerators," 2021, IEEE Internet of Things Journal
  • "A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms," 2025, ACM Computing Surveys

The scientist has also contributed to book publications, including works published by Springer International Publishing. One such work is the "Second International Conference on Networks and Advances in Computational Technologies," published in 2021.

Best Publications

  • Noxim: An open, extensible and cycle-accurate network on chip simulator

    Vincenzo Catania;Andrea Mineo;Salvatore Monteleone;Maurizio Palesi

  • Multi-objective mapping for mesh-based NoC architectures

    Giuseppe Ascia;Vincenzo Catania;Maurizio Palesi

  • Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip

    Giuseppe Ascia;Vincenzo Catania;Maurizio Palesi;Davide Patti

  • Multi-objective design space exploration using genetic algorithms

    Maurizio Palesi;Tony Givargis

  • Cycle-Accurate Network on Chip Simulation with Noxim

    Vincenzo Catania;Andrea Mineo;Salvatore Monteleone;Maurizio Palesi

  • Application Specific Routing Algorithms for Networks on Chip

    M. Palesi;R. Holsmark;S. Kumar;V. Catania

  • Routing Algorithms in Networks-on-Chip

    Maurizio Palesi;Masoud Daneshtalab

  • A methodology for design of application specific deadlock-free routing algorithms for NoC systems

    Maurizio Palesi;Rickard Holsmark;Shashi Kumar;Vincenzo Catania

  • Efficient design space exploration for application specific systems-on-a-chip

    Giuseppe Ascia;Vincenzo Catania;Alessandro G. Di Nuovo;Maurizio Palesi

  • HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks

    Masoumeh Ebrahimi;Masoud Daneshtalab;Fahimeh Farahnakian;Juha Plosila

  • Data Encoding Schemes in Networks on Chip

    Maurizio Palesi;Giuseppe Ascia;Fabrizio Fazzino;Vincenzo Catania

  • Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs

    A. Mejia;M. Palesi;J. Flich;S. Kumar

  • A GA-based design space exploration framework for parameterized system-on-a-chip platforms

    G. Ascia;V. Catania;M. Palesi

  • Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip

    Nima Jafarzadeh;Maurizio Palesi;Ahmad Khademzadeh;Ali Afzali-Kusha

  • A method for router table compression for application specific routing in mesh topology noc architectures

    Maurizio Palesi;Shashi Kumar;Rickard Holsmark

  • A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip.

    Giuseppe Ascia;Vincenzo Catania;Maurizio Palesi

  • An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators

    Seyed Morteza Nabavinejad;Mohammad Baharloo;Kun-Chih Chen;Maurizio Palesi

  • On self-tuning networks-on-chip for dynamic network-flow dominance adaptation

    Xiaohang Wang;Mei Yang;Yingtao Jiang;Peng Liu

  • Mapping Cores on Network-on-Chip

    Giuseppe Ascia;Vincenzo Catania;Maurizio Palesi

  • Neighbors-on-Path: A New Selection Strategy for On-Chip Networks

    Giuseppe Ascia;Vincenzo Catania;Maurizio Palesi;Davide Patti

  • EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration.

    Giuseppe Ascia;Vincenzo Catania;Maurizio Palesi;Davide Patti

  • A New Selection Strategy for On-Chip Networks

    Giuseppe Ascia;Vincenzo Catania;Maurizio Palesi;Davide Patti

Frequent Co-Authors

Masoud Daneshtalab
Masoud Daneshtalab Mälardalen University
Juha Plosila
Juha Plosila University of Turku
José Duato
José Duato Universitat Politècnica de València
Alex Yakovlev
Alex Yakovlev Newcastle University
Pedro López
Pedro López Universitat Politècnica de València
Hannu Tenhunen
Hannu Tenhunen Royal Institute of Technology
Pasi Liljeberg
Pasi Liljeberg University of Turku
Ali Afzali-Kusha
Ali Afzali-Kusha University of Tehran
Jose Flich
Jose Flich Universitat Politècnica de València
Radu Marculescu
Radu Marculescu The University of Texas at Austin

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