2020 - IEEE Fellow For contributions to network-on-chip architectures for manycore computing
Partha Pratim Pande spends much of his time researching Network on a chip, Embedded system, System on a chip, Interconnection and Wireless. His work carried out in the field of Network on a chip brings together such families of science as Integrated circuit design, Network topology and Integrated circuit. Partha Pratim Pande combines subjects such as Crosstalk, Latency, Multi-core processor and Packet switching with his study of Embedded system.
Within one scientific family, Partha Pratim Pande focuses on topics pertaining to Efficient energy use under Multi-core processor, and may sometimes address concerns connected to Energy conservation, Wi-Fi array and Bandwidth. His System on a chip study integrates concerns from other disciplines, such as Network architecture and Routing. He frequently studies issues relating to Computer architecture and Interconnection.
His primary scientific interests are in Embedded system, Network on a chip, Wireless, Multi-core processor and Interconnection. His work in the fields of Embedded system, such as System on a chip, intersects with other areas such as Dissipation and Scalability. His Network on a chip research incorporates elements of Integrated circuit design, Computer architecture and Very-large-scale integration.
His research integrates issues of Computer network, Latency, Data transmission and Electronic engineering in his study of Wireless. The Multi-core processor study combines topics in areas such as Frequency scaling, Hardware acceleration, Distributed computing and Robustness. The study incorporates disciplines such as Fault tolerance and Network topology in addition to Interconnection.
Partha Pratim Pande spends much of his time researching Distributed computing, Key, Electronic engineering, Design space exploration and Computer architecture. His research in Distributed computing intersects with topics in Energy consumption and Network on a chip. Many of his studies involve connections with topics such as System on a chip and Network on a chip.
The various areas that Partha Pratim Pande examines in his Electronic engineering study include Switched capacitor, Topology, Voltage regulator and Electrical efficiency. Partha Pratim Pande interconnects Airfield traffic pattern, Latency and Parallel computing in the investigation of issues within Design space exploration. His Computer architecture research is multidisciplinary, incorporating elements of Artificial neural network, Transistor and Resistive random-access memory.
Partha Pratim Pande mostly deals with Distributed computing, Network on a chip, Computer architecture, Efficient energy use and Systems design. His studies deal with areas such as Interconnection and Design space exploration as well as Distributed computing. His Network on a chip investigation overlaps with other areas such as Space exploration and Adaptive design.
He usually deals with Computer architecture and limits it to topics linked to Convolutional neural network and System on a chip, Deep learning, Telecommunications network and Wireless sensor network. His biological study spans a wide range of topics, including Energy consumption and Embedded system. His work in the fields of Integrated circuit design overlaps with other areas such as Context.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Performance evaluation and design trade-offs for network-on-chip interconnect architectures
Partha Pratim Pande;C. Grecu;M. Jones;A. Ivanov.
IEEE Transactions on Computers (2005)
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
B.S. Feero;P.P. Pande.
IEEE Transactions on Computers (2009)
System-on-Chip: Reuse and Integration
R. Saleh;S. Wilton;S. Mirabbasi;A. Hu.
Proceedings of the IEEE (2006)
Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems
A. Ganguly;K. Chang;S. Deb;P. P. Pande.
IEEE Transactions on Computers (2011)
Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges
S. Deb;A. Ganguly;P. P. Pande;B. Belzer.
IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2012)
Design of a switch for network on chip applications
P.P. Pande;C. Grecu;A. Ivanov;R. Saleh.
international symposium on circuits and systems (2003)
Design, synthesis, and test of networks on chips
P.P. Pande;C. Grecu;A. Ivanov;R. Saleh.
IEEE Design & Test of Computers (2005)
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
Luca P. Carloni;Partha Pande;Yuan Xie.
networks on chips (2009)
Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects
Sujay Deb;Kevin Chang;Xinmin Yu;Suman Prasad Sah.
IEEE Transactions on Computers (2013)
Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects
A. Ganguly;P.P. Pande;B. Belzer.
IEEE Transactions on Very Large Scale Integration Systems (2009)
Profile was last updated on December 6th, 2021.
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The ranking h-index is inferred from publications deemed to belong to the considered discipline.
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