World's Best Scientists 2026 revealed!
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Computer Science
USA
2026
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Electronics and Electrical Engineering
USA
2026

D-Index & Metrics

Computer Science

D-Index
122
Citations
55758
World Ranking
141
National Ranking
81

Electronics and Electrical Engineering

D-Index
123
Citations
56834
World Ranking
55
National Ranking
30

Research.com Recognitions

  • 2026 - Research.com Computer Science in United States Leader Award
  • 2026 - Research.com Electronics and Electrical Engineering in United States Leader Award
  • 2025 - Research.com Computer Science in United States Leader Award
  • 2025 - Research.com Electronics and Electrical Engineering in United States Leader Award
  • 2022 - Research.com Computer Science in United States Leader Award
  • 2011 - Semiconductor Industry Association University Researcher Award
  • 2008 - Fellow of the American Academy of Arts and Sciences
  • 2007 - Member of the National Academy of Engineering For leadership in high-bandwidth memory-interface technology and in scalable cache-coherent multiprocessor architectures.
  • 2006 - IEEE Donald O. Pederson Award in Solid-State Circuits “For pioneering contributions to the design of high-performance digital integrated circuits and systems.”
  • 2003 - ACM Fellow For contributions to multiprocessor architecture.

Overview

Mark Horowitz is affiliated with Stanford University in the United States and has contributed extensively to research in computer science and engineering. Their research primarily focuses on hardware and architecture, with significant contributions in areas such as embedded systems design techniques and parallel computing and optimization.

The scientist's work spans multiple subfields, including:

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Computer Networks and Communications
  • Artificial Intelligence
  • Surgery

Mark Horowitz's main topics of interest include:

  • Embedded Systems Design Techniques
  • Parallel Computing and Optimization Techniques
  • Interconnection Networks and Systems
  • VLSI and Analog Circuit Testing
  • VLSI and FPGA Design Techniques
  • CCD and CMOS Imaging Sensors
  • Scientific Computing and Data Management

Key recent papers authored or co-authored by Mark Horowitz include:

  • AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers, 2022, ACM Transactions on Embedded Computing Systems
  • Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
  • Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators, 2022, ACM Transactions on Architecture and Code Optimization
  • An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Amber: A 16-nm System-on-Chip With a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra, 2023, IEEE Journal of Solid-State Circuits

Frequent publication venues where Mark Horowitz's research appears include:

  • arXiv (Cornell University)
  • IEEE Journal of Solid-State Circuits
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Proceedings of the 59th ACM/IEEE Design Automation Conference
  • Journal of Pediatric Urology

Mark Horowitz often collaborates with a number of co-authors, including:

  • Priyanka Raina (16 publications)
  • Keyi Zhang (12 publications)
  • Christopher Torng (11 publications)
  • Jackson Melchert (9 publications)
  • Qiaoyi Liu (9 publications)

The scientist has been recognized through several awards, including:

  • Semiconductor Industry Association University Researcher Award, 2011
  • Fellow of the American Academy of Arts and Sciences, 2008
  • Member of the National Academy of Engineering, 2007, for leadership in high-bandwidth memory-interface technology and in scalable cache-coherent multiprocessor architectures
  • IEEE Donald O. Pederson Award in Solid-State Circuits, 2006, for pioneering contributions to the design of high-performance digital integrated circuits and systems
  • ACM Fellow, 2003, for contributions to multiprocessor architecture

Best Publications

  • Light field photography with a hand-held plenoptic camera

    Ren Ng;Marc Levoy;Mathieu Br;Gene Duval

  • EIE: efficient inference engine on compressed deep neural network

    Song Han;Xingyu Liu;Huizi Mao;Jing Pu

  • 1.1 Computing's energy problem (and what we can do about it)

    Mark Horowitz

  • The future of wires

    R. Ho;K.W. Mai;M.A. Horowitz

  • The Stanford Dash multiprocessor

    D. Lenoski;J. Laudon;K. Gharachorloo;W.-D. Weber

  • High performance imaging using large camera arrays

    Bennett Wilburn;Neel Joshi;Vaibhav Vaish;Eino-Ville Talvala

  • Signal Delay in RC Tree Networks

    J. Rubinstein;P. Penfield;M.A. Horowitz

  • Light field microscopy

    Marc Levoy;Ren Ng;Andrew Adams;Matthew Footer

  • Forwarding metamorphosis: fast programmable match-action processing in hardware for SDN

    Pat Bosshart;Glen Gibb;Hun-Seok Kim;George Varghese

  • Architectural support for copy and tamper-resistant software

    David Lie Chandramohan Thekkath;Mark Mitchell;Patrick Lincoln;Dan Boneh

  • Energy dissipation in general purpose microprocessors

    R. Gonzalez;M. Horowitz

  • An evaluation of directory schemes for cache coherence

    Anant Agarwal;Richard Simoni;John Hennessy;Mark Horowitz

  • Supply and threshold voltage scaling for low power CMOS

    R. Gonzalez;B.M. Gordon;M.A. Horowitz

  • Integrated circuit I/O using a high performance bus interface

    Michael Farmwald;Mark Horowitz

  • Understanding sources of inefficiency in general-purpose chips

    Rehan Hameed;Wajahat Qadeer;Megan Wachs;Omid Azizi

  • The Stanford FLASH multiprocessor

    Jeffrey Kuskin;David Ofelt;Mark Heinrich;John Heinlein

  • A semidigital dual delay-locked loop

    S. Sidiropoulos;M.A. Horowitz

  • Smart Memories: a modular reconfigurable architecture

    Ken Mai;Tim Paaske;Nuwan Jayasena;Ron Ho

  • Clustered voltage scaling technique for low-power design

    Kimiyoshi Usami;Mark Horowitz

  • Precise delay generation using coupled oscillators

    J.G. Maneatis;M.A. Horowitz

Frequent Co-Authors

Jared L. Zerbe
Jared L. Zerbe Apple (United States)
Kevin S. Donnelly
Kevin S. Donnelly Rambus (United Kingdom)
Vladimir Stojanovic
Vladimir Stojanovic University of California, Berkeley
Elad Alon
Elad Alon University of California, Berkeley
Craig E. Hampel
Craig E. Hampel Rambus (United Kingdom)
John L. Hennessy
John L. Hennessy Stanford University
Marc Levoy
Marc Levoy Google (United States)
Christos Kozyrakis
Christos Kozyrakis Stanford University
Pat Hanrahan
Pat Hanrahan Stanford University
Chih-Kong Ken Yang
Chih-Kong Ken Yang University of California, Los Angeles

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