Kevin S. Donnelly

Overview

Best Publications

• Memory controller that calibrates a transmit timing offset

  Jared LeVan Zerbe;Kevin S. Donnelly;Stefanos Sidiropoulos;Donald C. Stark

  597
  Citations

• Multi-PAM Output Driver with Distortion Compensation

  Jared L. Zerbe;Bruno W. Garlepp;Pak S. Chau;Kevin S. Donnelly

  447
  Citations

• Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell

  J. Zerbe;C. Werner;V. Stojanovic;F. Chen

  389
  Citations

• A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM

  T.H. Lee;K.S. Donnelly;J.T.C. Ho;J. Zerbe

  377
  Citations

• A portable digital DLL for high-speed CMOS interface circuits

  B.W. Garlepp;K.S. Donnelly;Jun Kim;P.S. Chau

  376
  Citations

• Chip having port to receive value that represents adjustment to output driver parameter

  Mark A. Horowitz;Craig E. Hampel;Alfredo Moncayo;Kevin S. Donnelly

  324
  Citations

• High-speed signaling systems with adaptable pre-emphasis and equalization

  Jared L. Zerbe;Fred F. Chen;Andrew Ho;Ramin Farjad-Rad

  207
  Citations

• Voltage controlled phase shifter with unlimited range

  Thomas H. Lee;Kevin S. Donnelly;Tsyr-Chyang Ho

  178
  Citations

• A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

  K.-Y.K. Chang;J. Wei;C. Huang;S. Li

  148
  Citations

• Chip-to-chip communication system using an ac-coupled bus and devices employed in same

  Donald V. Perino;Haw-Jyh Liaw;Alfredo Moncayo;Kevin Donnelly

  145
  Citations

• Output driver circuit with well-controlled output impedance

  Bruno Werner Garlepp;Kevin S. Donnelly;Jared LeVan Zerbe

  143
  Citations

• Transceiver with latency alignment circuitry

  Kevin Donnelly;Mark Johnson;Chanh Tran;John B. Dillon

  142
  Citations

• Amplifier with active duty cycle correction

  Thomas H. Lee;Kevin S. Donnelly;Tsyr-Chyang Ho

  137
  Citations

• Circuitry for the delay adjustment of a clock signal

  Kevin S. Donnelly;Jun Kim;Bruno W. Garleep;Mark A. Horowitz

  123
  Citations

• Variable delay element

  Bruno Werner Garlepp;Pak Shing Chau;Kevin S. Donnelly;Clemenz Portmann

  121
  Citations

• Differential comparator for amplifying small swing signals to a full swing output

  Thomas H. Lee;Kevin S. Donnelly

  113
  Citations

• Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell

  Unknown

  109
  Citations

• Apparatus and method for generating a distributed clock signal

  Frederick A. Ware;Kevin S. Donnelly;Ely K. Tsern;Srinivas Nimmagadda

  107
  Citations

• A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers

  J.L. Zerbe;P.S. Chau;C.W. Werner;W.F. Stonecypher

  81
  Citations

• 1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus

  J.L. Zerbe;P.S. Chau;C.W. Werner;T.P. Thrush

  81
  Citations

• Bus driver circuit including a slew rate indicator circuit having a one shot circuit

  Kevin S. Donnelly;Chanh Tran;Michael Ching;Bruno Garlepp

  80
  Citations

• A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

  K.-Y.K. Chang;J. Wei;S. Li;Y. Li

  22
  Citations