James E. Jaussi

Best Publications

• A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS

  G. Balamurugan;J. Kennedy;G. Banerjee;J.E. Jaussi

  201
  Citations

• An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew

  J.E. Jaussi;G. Balamurugan;D.R. Johnson;B.K. Casper

  157
  Citations

• Co-Packaged Photonics for High Performance Computing: Status, Challenges and Opportunities

  Unknown

  130
  Citations

• An 8-Gb/s simultaneous bidirectional link with on-die waveform capture

  B. Casper;A. Martin;J.E. Jaussi;J. Kennedy

  126
  Citations

• A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B.

  B. Casper;J. Jaussi;F. O'Mahony;M. Mansuri

  118
  Citations

• Modeling and Analysis of High-Speed I/O Links

  G. Balamurugan;B. Casper;J.E. Jaussi;M. Mansuri

  117
  Citations

• A Scalable 0.128–1 Tb/s, 0.8–2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS

  Mozhgan Mansuri;James E. Jaussi;Joseph T. Kennedy;Tzu-Chien Hsueh

  109
  Citations

• Strong Injection Locking in Low- $Q$ LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver

  S. Shekhar;G. Balamurugan;D.J. Allstot;M. Mansuri

  92
  Citations

• A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control

  Hao Li;Ganesh Balamurugan;Taehwan Kim;Meer N. Sakib

  88
  Citations

• A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems

  Unknown

  86
  Citations

• A 47 $\, imes\,$ 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS

  Frank O'Mahony;James E Jaussi;Joseph Kennedy;Ganesh Balamurugan

  85
  Citations

• Future Microprocessor Interfaces: Analysis, Design and Optimization

  B. Casper;G. Balamurugan;J.E. Jaussi;J. Kennedy

  80
  Citations

• A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS

  Tawfiq Musah;James E. Jaussi;Ganesh Balamurugan;Sami Hyvonen

  66
  Citations

• The future of electrical I/O for microprocessors

  Frank O'Mahony;Ganesh Balamurugan;James E. Jaussi;Joseph Kennedy

  65
  Citations

• A 112 Gb/s PAM4 Silicon Photonics Transmitter With Microring Modulator and CMOS Driver

  Hao Li;Bryan Casper;Ganesh Balamurugan;Meer Sakib

  65
  Citations

• A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS

  F. O'Mahony;S. Shekhar;M. Mansuri;G. Balamurugan

  59
  Citations

• Silicon Photonic Microring-Based 4 × 112 Gb/s WDM Transmitter With Photocurrent-Based Thermal Control in 28-nm CMOS

  Unknown

  59
  Citations

• A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS

  Hao Li;Ganesh Balamurugan;James Jaussi;Bryan Casper

  53
  Citations

• A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS

  Unknown

  49
  Citations

• A 60-GHz Transceiver and Baseband With Polarization MIMO in 28-nm CMOS

  Kaushik Dasgupta;Saeid Daneshgar;Chintan Thakkar;Shinwon Kang

  45
  Citations