Glenn J. Hinton mainly focuses on Computer hardware, Parallel computing, Memory map, Embedded system and Semiconductor memory. His Computer hardware study combines topics in areas such as Signal and Cache. Glenn J. Hinton combines subjects such as Page and Virtual memory, Zero page, Demand paging, Page attribute table with his study of Memory map.
His studies in Embedded system integrate themes in fields like Load/store architecture, Power management, Modular design, Systems architecture and Point-to-point. His study on Load/store architecture also encompasses disciplines like
Glenn J. Hinton mostly deals with Computer hardware, Parallel computing, Operating system, Cache and Microprocessor. His work in Instruction register, Cycles per instruction, Semiconductor memory, Registered memory and Register file are all subfields of Computer hardware research. Glenn J. Hinton works mostly in the field of Parallel computing, limiting it down to concerns involving Operand and, occasionally, Register.
In his research, Instruction stream and Decodes is intimately related to State, which falls under the overarching field of Operating system. His study in Microprocessor is interdisciplinary in nature, drawing from both Page table, Source data, Translation lookaside buffer and Re-order buffer. As part of the same scientific family, he usually focuses on Out-of-order execution, concentrating on Load/store architecture and intersecting with Embedded system.
His primary areas of investigation include Computer hardware, Operating system, Cache, Memory map and Registered memory. His Computer hardware study incorporates themes from Controller, Process and Metadata. He focuses mostly in the field of Operating system, narrowing it down to matters related to State and, in some cases, Abort and Firmware.
He has researched Cache in several fields, including Logical block addressing, Heuristics and Electrical engineering. In his research on the topic of Memory map, Memory refresh and Volatile memory is strongly related with Interleaved memory. His CPU cache study is associated with Parallel computing.
The scientist’s investigation covers issues in Computer hardware, Memory map, Interleaved memory, Computer memory and Registered memory. The concepts of his Computer hardware study are interwoven with issues in Metadata and Code. His Memory map research includes themes of Page and Virtual memory, Zero page, Demand paging, Page attribute table.
His studies deal with areas such as Memory refresh, Volatile memory and Flat memory model as well as Interleaved memory. His research investigates the connection with Volatile memory and areas like Embedded system which intersect with concerns in Computer architecture. His work deals with themes such as Mechanism, Random access memory, Parallel computing, Controller and Block, which intersect with Non-volatile random-access memory.
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A family of 45nm IA processors
Rajesh Kumar;Glenn Hinton.
international solid-state circuits conference (2009)
Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
James M Brayton;Michael W Rhodehamel;Nitin V Sarangdhar;Glenn J Hinton.
Processor ordering consistency for a processor performing out-of-order instruction execution
Abramson Jeffrey M;Akkary Haitham;Glew Andrew F;Hinton Glenn J.
Pipeline process of instructions in a computer system
Hinton Glenn J;Papworth David B;Glew Andrew F;Fetterman Michael A.
Circuit and method for scheduling instructions by predicting future availability of resources required for execution
Andrew F. Glew;Darrell D. Boggs;Michael A. Fetterman;Glenn J. Hinton.
Method and apparatus for implementing a set-associative branch target buffer
Bradley D. Hoyt;Glenn J. Hinton;David B. Papworth;Ashwani Kumar Gupta.
Trace based instruction caching
Robert F. Krick;Glenn J. Hinton;Michael D. Upton;David J. Sager.
Two-level system main memory
Eric J. Dahlen;Glenn J. Hinton;Raj K. Ramanujan.
Apparatus and method for implementing a multi-level memory hierarchy
Raj K. Ramanujan;Rajat Agarwal;Kai Cheng;Taarinya Polepeddi.
Apparatus, method, and system for implementing micro page tables
Glenn Hinton;Raj Ramanujan;Scott J. Cape;Madhavan Parthasarathy.
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