World's Best Scientists 2026 revealed!

D-Index & Metrics

Computer Science

D-Index
52
Citations
6524
World Ranking
5182
National Ranking
2375

Overview

What is he best known for?

The fields of study he is best known for:

  • Operating system
  • Central processing unit
  • Microprocessor

Glenn J. Hinton mainly focuses on Computer hardware, Parallel computing, Memory map, Embedded system and Semiconductor memory. His Computer hardware study combines topics in areas such as Signal and Cache. Glenn J. Hinton combines subjects such as Page and Virtual memory, Zero page, Demand paging, Page attribute table with his study of Memory map.

His studies in Embedded system integrate themes in fields like Load/store architecture, Power management, Modular design, Systems architecture and Point-to-point. His study on Load/store architecture also encompasses disciplines like

  • Memory operation together with Blocking,
  • Invalid Data which connect with Out-of-order execution and State. Glenn J. Hinton focuses mostly in the field of Reservation station, narrowing it down to topics relating to Scoreboarding and, in certain cases, Execution unit and CPU cache.

His most cited work include:

  • Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue (202 citations)
  • Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer (197 citations)
  • Processor ordering consistency for a processor performing out-of-order instruction execution (190 citations)

What are the main themes of his work throughout his whole career to date?

Glenn J. Hinton mostly deals with Computer hardware, Parallel computing, Operating system, Cache and Microprocessor. His work in Instruction register, Cycles per instruction, Semiconductor memory, Registered memory and Register file are all subfields of Computer hardware research. Glenn J. Hinton works mostly in the field of Parallel computing, limiting it down to concerns involving Operand and, occasionally, Register.

In his research, Instruction stream and Decodes is intimately related to State, which falls under the overarching field of Operating system. His study in Microprocessor is interdisciplinary in nature, drawing from both Page table, Source data, Translation lookaside buffer and Re-order buffer. As part of the same scientific family, he usually focuses on Out-of-order execution, concentrating on Load/store architecture and intersecting with Embedded system.

He most often published in these fields:

  • Computer hardware (43.65%)
  • Parallel computing (25.41%)
  • Operating system (19.34%)

What were the highlights of his more recent work (between 2008-2020)?

  • Computer hardware (43.65%)
  • Operating system (19.34%)
  • Cache (16.57%)

In recent papers he was focusing on the following fields of study:

His primary areas of investigation include Computer hardware, Operating system, Cache, Memory map and Registered memory. His Computer hardware study incorporates themes from Controller, Process and Metadata. He focuses mostly in the field of Operating system, narrowing it down to matters related to State and, in some cases, Abort and Firmware.

He has researched Cache in several fields, including Logical block addressing, Heuristics and Electrical engineering. In his research on the topic of Memory map, Memory refresh and Volatile memory is strongly related with Interleaved memory. His CPU cache study is associated with Parallel computing.

Between 2008 and 2020, his most popular works were:

  • A family of 45nm IA processors (153 citations)
  • Apparatus, method, and system for implementing micro page tables (87 citations)
  • Apparatus and method for implementing a multi-level memory hierarchy (86 citations)

In his most recent research, the most cited papers focused on:

  • Operating system
  • Central processing unit
  • Microprocessor

The scientist’s investigation covers issues in Computer hardware, Memory map, Interleaved memory, Computer memory and Registered memory. The concepts of his Computer hardware study are interwoven with issues in Metadata and Code. His Memory map research includes themes of Page and Virtual memory, Zero page, Demand paging, Page attribute table.

His studies deal with areas such as Memory refresh, Volatile memory and Flat memory model as well as Interleaved memory. His research investigates the connection with Volatile memory and areas like Embedded system which intersect with concerns in Computer architecture. His work deals with themes such as Mechanism, Random access memory, Parallel computing, Controller and Block, which intersect with Non-volatile random-access memory.

Best Publications

  • A family of 45nm IA processors

    Rajesh Kumar;Glenn Hinton

  • Computersystem und Verfahren zum Aufrechterhalten der Speicherkonsistenz in einer Busanforderungswarteschlange

    James M Brayton;Michael W Rhodehamel;Nitin V Sarangdhar;Glenn J Hinton

  • Pipeline process of instructions in a computer system

    Hinton Glenn J;Papworth David B;Glew Andrew F;Fetterman Michael A

  • Method and apparatus for implementing a branch target buffer in CISC processor

    Bradley D. Hoyt;Glenn J. Hinton;David B. Papworth;Ashwani Kumar Gupta

  • Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor

    Bradley D. Hoyt;Glenn J. Hinton;David B. Papworth;Ashwani Kumar Gupta

  • Mechanism for efficiently overlapping multiple operand types in a microprocessor

    Andrew F. Glew;Darrell D. Boggs;Michael A. Fetterman;Glenn J. Hinton

  • Trace based instruction caching

    Robert F. Krick;Glenn J. Hinton;Michael D. Upton;David J. Sager

  • Equipment and method for realizing multi-level memory hierarchical structure with different operation modes

    Ramanujan Raj K;Agarwal Rajat;Hinton Glenn J

  • Apparatus, method, and system for implementing micro page tables

    Glenn Hinton;Raj Ramanujan;Scott J. Cape;Madhavan Parthasarathy

  • Apparatus and method for implementing a multi-level memory hierarchy

    Raj K. Ramanujan;Rajat Agarwal;Kai Cheng;Taarinya Polepeddi

  • Two-level system main memory

    Eric J. Dahlen;Glenn J. Hinton;Raj K. Ramanujan

  • Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed

    David B. Papworth;Andrew F. Glew;Michael A. Fetterman;Glenn J. Hinton

  • Processor having execution core sections operating at different clock rates

    David J. Sager;Thomas D. Fletcher;Glenn J. Hinton;Michael D. Upton

  • Staggering execution of a single packed data instruction using the same circuit

    Patrice Roussel;Glenn J. Hinton;Shreekant S. Thakkar;Brent R. Boswell

  • CACHE DE BLOCS DE DONNEES EMPILES SUR UNE PUCE DE MICROPROCESSEUR

    Myers Glenford J;Lai Konrad;Imel Michael T;Hinton Glenn

  • Flag renaming and flag masks within register alias table

    Robert P. Colwell;Andrew F. Glew;Atiq A. Bajwa;Glenn J. Hinton

  • Method and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessor

    Robert P. Colwell;Atiq Bajwa;Michael A. Fetterman;Andrew F. Glew

  • Method and apparatus for processing memory-type information within a microprocessor

    Andrew F. Apartment Glew;Glenn J. Hinton

  • Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations

    Jeffrey M. Abramson;David B. Papworth;Haitham H. Akkary;Andrew F. Glew

  • Method and apparatus for implementing a single clock cycle line replacement in a data cache unit

    Haitham Akkary;Mandar S. Joshi;Rob Murray;Brent E. Lince

Frequent Co-Authors

David B. Papworth
David B. Papworth Intel (United States)
Michael A. Rothman
Michael A. Rothman Intel (United States)
Vincent J. Zimmer
Vincent J. Zimmer Intel (United States)
Konrad K. Lai
Konrad K. Lai Intel (United States)
Alaa R. Alameldeen
Alaa R. Alameldeen Intel (United States)
Richard Uhlig
Richard Uhlig Intel (United States)
Shubhendu S. Mukherjee
Shubhendu S. Mukherjee Cavium (United States)
Gilbert Neiger
Gilbert Neiger Intel (United States)
Mark T. Bohr
Mark T. Bohr Intel (United States)

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