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Alexandre E. Eichenberger

Alexandre E. Eichenberger

D-Index & Metrics

Computer Science

D-Index
35
Citations
4353
World Ranking
11807
National Ranking
4821

Overview

Alexandre E. Eichenberger is affiliated with IBM in the United States. Their research work spans multiple areas within computer science, with a particular focus on hardware and architecture subfields. The main topics covered in their work include parallel computing and optimization techniques, embedded systems design techniques, interconnection networks and systems, advanced neural network applications, graph theory and algorithms, and software system performance and reliability.

The scientist has contributed to several recent publications. Notable papers include:

  • "Compiling ONNX Neural Network Models Using MLIR," published in 2020 in arXiv (Cornell University)
  • "Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption," published in 2020 in IEEE Transactions on Computers
  • "Serving Deep Learning Model in Relational Databases," published in 2023 in arXiv (Cornell University)

Eichenberger frequently collaborates with several co-authors. These include Cristobal Ortega, Lluc Alvarez, Marc Casas, Ramon Bertran, and Alper Buyuktosunoglu.

Their publication venues primarily consist of:

  • arXiv (Cornell University)
  • IEEE Transactions on Computers

Within their field of study, they have contributed mainly to computer science with specific emphasis on hardware and architecture, computer networks and communications, and computer vision and pattern recognition.

The research outputs indicate a cross-disciplinary approach integrating aspects of parallel computing, system optimization, and neural networks, alongside an interest in the application of these technologies within embedded systems and relational databases.

Best Publications

  • Multi-petascale highly efficient parallel supercomputer

    Sameh Asaad;Ralph E. Bellofatto;Michael A. Blocksome;Matthias A. Blumrich

  • Vectorization for SIMD architectures with alignment constraints

    Alexandre E. Eichenberger;Peng Wu;Kevin O'Brien

  • Optimizing Compiler for the CELL Processor

    A.E. Eichenberger;K. O'Brien;Peng Wu;Tong Chen

  • Using advanced compiler technology to exploit the performance of the Cell Broadband Engine TM architecture

    A. E. Eichenberger;J. K. O'Brien;K. M. O'Brien;P. Wu

  • OMPT: An OpenMP Tools Application Programming Interface for Performance Analysis

    Alexandre E. Eichenberger;John M. Mellor-Crummey;Martin Schulz;Michael Wong

  • Efficient SIMD Code Generation for Runtime Alignment and Length Conversion

    Peng Wu;Alexandre E. Eichenberger;Amy Wang

  • Effective cluster assignment for modulo scheduling

    Erik Nystrom;Alexandre E. Eichenberger

  • Framework for generating mixed-mode operations in loop-level simdization

    Alexandre E. Eichenberger;Kai-Ting Amy Wang;Peng Wu

  • Stage scheduling: a technique to reduce the register requirements of a module schedule

    Alexandre E. Eichenberger;Edward S. Davidson

  • An integrated simdization framework using virtual vectors

    Peng Wu;Alexandre E. Eichenberger;Amy Wang;Peng Zhao

  • Optimum modulo schedules for minimum register requirements

    Alexandre E. Eichenberger;Edward S. Davidson;Santosh G. Abraham

  • Efficient formulation for optimal modulo schedulers

    Alexandre E. Eichenberger;Edward S. Davidson

  • Coordinating GPU threads for OpenMP 4.0 in LLVM

    Carlo Bertolli;Samuel F. Antao;Alexandre E. Eichenberger;Kevin O'Brien

  • Automatic creation of tile size selection models

    Tomofumi Yuki;Lakshminarayanan Renganarayanan;Sanjay Rajopadhye;Charles Anderson

  • Hybrid access-specific software cache techniques for the cell BE architecture

    Marc Gonzalez;Nikola Vujic;Xavier Martorell;Eduard Ayguade

  • Complex Matrix Multiplication Operations with Data Pre-Conditioning in a High Performance Computing Architecture

    Alexandre E. Eichenberger;Michael K. Gschwind;John A. Gunnels

  • Efficient Code Generation Using Loop Peeling for SIMD Loop Code with Multiple Misaligned Statements

    Alexandre E. Eichenberger;Kai-Ting Amy Wang;Peng Wu

  • Minimum register requirements for a module schedule

    Alexandre E. Eichenberger;Edward S. Davidson;Santosh G. Abraham

  • System and Method for Domain Stretching for an Advanced Dual-Representation Polyhedral Loop Transformation Framework

    Alexandre E. Eichenberger;John K. P. O'Brien;Kathryn M. O'Brien;Nicolas T. Vasilache

  • Register allocation for predicated code

    Alexandre E. Eichenberger;Edward S. Davidson

Frequent Co-Authors

Michael Karl Gschwind
Michael Karl Gschwind IBM (United States)
Alan Gara
Alan Gara IBM (United States)
Edward S. Davidson
Edward S. Davidson University of Michigan–Ann Arbor
John A. Gunnels
John A. Gunnels Nvidia (United States)
Valentina Salapura
Valentina Salapura Google (United States)
Xavier Martorell
Xavier Martorell Universitat Politècnica de Catalunya
Eduard Ayguadé
Eduard Ayguadé Barcelona Supercomputing Center
Jesús Labarta
Jesús Labarta Barcelona Supercomputing Center
Bronis R. de Supinski
Bronis R. de Supinski Lawrence Livermore National Laboratory
Pradip Bose
Pradip Bose IBM (United States)

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