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Computer Science

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35
Citations
7086
World Ranking
11523
National Ranking
4734

Research.com Recognitions

  • 2009 - IEEE Fellow For leadership in high performance, multithreaded processor architectures

Overview

Balaram Sinharoy is affiliated with IBM in the United States. Their professional career is connected to this primary institution, where they have contributed to the fields of computer architecture and related areas.

Among the achievements attributed to Balaram Sinharoy is the distinction of being named an IEEE Fellow in 2009. This recognition was granted for leadership in high performance, multithreaded processor architectures.

While specific details on recent papers, co-authors, publication venues, and book publications are not listed, Balaram Sinharoy's work is closely associated with the development and advancement of multithreaded and high-performance processors, a specialized area within computing hardware research.

Details on exact fields of study, subfields, or main research topics have not been provided, but the IEEE Fellow citation highlights a focus on processor architecture. This suggests involvement in areas such as:

  • High-performance computing
  • Multithreaded processor design

Balaram Sinharoy's professional record reflects notable contributions within the industrial research context of IBM, primarily in the United States. This affiliation indicates experience with applied research and development in computer engineering and architecture.

Best Publications

  • POWER4 system microarchitecture

    J. M. Tendler;J. S. Dodson;J. S. Fields;H. Le

  • IBM Power5 chip: a dual-core multithreaded processor

    R. Kalla;Balaram Sinharoy;J.M. Tendler

  • POWER5 System microarchitecture

    B. Sinharoy;R. N. Kalla;J. M. Tendler;R. J. Eickemeyer

  • Power7: IBM's Next-Generation Server Processor

    Ron Kalla;Balaram Sinharoy;William J Starke;Michael Floyd

  • IBM POWER8 processor core microarchitecture

    B. Sinharoy;J. A. Van Norstrand;R. J. Eickemeyer;H. Q. Le

  • IBM POWER7 multicore server processor

    B. Sinharoy;R. Kalla;W. J. Starke;H. Q. Le

  • Design and implementation of the POWER5/spl trade/ microprocessor

    J. Clabes;J. Friedrich;M. Sweet;J. Dilullo

  • Design and implementation of the POWER5 microprocessor

    Joachim Clabes;Joshua Friedrich;Mark Sweet;Jack DiLullo

  • Method for resource balancing using dispatch flush in a simultaneous multithread processor

    William E. Burky;Richard J. Eickemeyer;Ronald N. Kalla;David S. Levitan

  • Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (smt) processor

    William Joseph Armstrong;Michael Stephen Floyd;Larry Scott Leitner;Ronald Nick Kalla

  • Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modes

    William Joseph Armstrong;Bruce G. Mealey;Naresh Nayar;Balaram Sinharoy

  • Method and system for dynamically shared completion table supporting multiple threads in a processing system

    Hung Qui Le;Peichun Liu;Balaram Sinharoy

  • Total flexibility of predicted fetching of multiple sectors from an aligned instruction cache for instruction execution

    Balaram Sinharoy

  • Method and logical apparatus for switching between single-threaded and multi-threaded execution states in a simultaneous multi-threaded (SMT) processor

    William Elton Burky;Michael Stephen Floyd;Ronald Nick Kalla;Balaram Sinharoy

  • The implementation of POWER7 TM : A highly parallel and scalable multi-core high-end server processor

    Dieter Wendel;Ronald Kalla;Robert Cargoni;Joachim Clables

  • Branch prediction apparatus and process for restoring replaced branch history for use in future branch predictions for an executing program

    Balaram Sinharoy

  • Method and logical apparatus for managing resource redistribution in a simultaneous multi-threaded (SMT) processor

    William Burky;Michael Floyd;Ronald Kalla;Balaram Sinharoy

  • Performance throttling for temperature reduction in a microprocessor

    Joachim Gerhard Clabes;Michael Stephen Floyd;Ronald Nick Kalla;Balaram Sinharoy

  • Method and apparatus for the dynamic creation of instructions utilizing a wide datapath

    Michael Gschwind;Balaram Sinharoy

  • Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions

    Balaram Sinharoy

  • Design and Implementation of the POWER5 TM Microprocessor

    Joachim Clabes;Joshua Friedrich;Mark Sweet;Jack DiLullo

Frequent Co-Authors

Ravi Kumar Arimilli
Ravi Kumar Arimilli IBM (United States)
Lixin Zhang
Lixin Zhang East China University of Science and Technology
Boleslaw K. Szymanski
Boleslaw K. Szymanski Rensselaer Polytechnic Institute
Robert W. Wisniewski
Robert W. Wisniewski Intel (United States)
Michael Karl Gschwind
Michael Karl Gschwind IBM (United States)
Phillip J. Restle
Phillip J. Restle IBM (United States)
Ramakrishnan Rajamony
Ramakrishnan Rajamony Goldman Sachs (United States)
Orran Krieger
Orran Krieger Boston University
Pradip Bose
Pradip Bose IBM (United States)
Guy Lynn Guthrie
Guy Lynn Guthrie IBM (United States)

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