World's Best Scientists 2026 revealed!

D-Index & Metrics

Computer Science

D-Index
37
Citations
4824
World Ranking
10904
National Ranking
4534

Overview

David B. Papworth is affiliated with Intel in the United States. Their professional activities are primarily connected to this organization based in the United States.

There are no recent papers listed under their name with titles, publication years, or specific venues available in the data provided.

Information regarding frequent co-authors is not present, indicating no identified recurring collaboration partners in the available data.

No frequent publication venues are documented, so there are no commonly targeted journals or conferences referenced for this scientist.

The source does not include any book publications or associated publishers connected to their work.

Details on main fields of study, subfields, or specific topics of research work have not been provided, meaning that no areas of scientific focus or specialization are documented here.

There are no recorded awards or honors attributed to David B. Papworth in the provided information.

Best Publications

  • A VLIW architecture for a trace scheduling compiler

    Robert P. Colwell;Robert P. Nix;John J. O'Donnell;David B. Papworth

  • Hierarchical priority branch handling for parallel execution in a parallel processor

    Robert P. Colwell;John O'Donnell;David B. Papworth;Paul K. Rodman

  • Pipeline process of instructions in a computer system

    Hinton Glenn J;Papworth David B;Glew Andrew F;Fetterman Michael A

  • Method and apparatus for implementing a branch target buffer in CISC processor

    Bradley D. Hoyt;Glenn J. Hinton;David B. Papworth;Ashwani Kumar Gupta

  • A VLIW architecture for a trace scheduling compiler

    Unknown

  • Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor

    Bradley D. Hoyt;Glenn J. Hinton;David B. Papworth;Ashwani Kumar Gupta

  • Mechanism for efficiently overlapping multiple operand types in a microprocessor

    Andrew F. Glew;Darrell D. Boggs;Michael A. Fetterman;Glenn J. Hinton

  • Instruction storage method with a compressed format using a mask word

    Robert P. Colwell;John O'Donnell;David B. Papworth;Paul K. Rodman

  • Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus

    Robert P. Colwell;John O'Donnell;David B. Papworth;Paul K. Rodman

  • Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed

    David B. Papworth;Andrew F. Glew;Michael A. Fetterman;Glenn J. Hinton

  • Virtual address table look aside buffer miss recovery method and apparatus

    Robert P. Colwell;John O'Donnell;David B. Papworth;Paul K. Rodman

  • Method and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessor

    Robert P. Colwell;Atiq Bajwa;Michael A. Fetterman;Andrew F. Glew

  • Tuning the Pentium Pro microarchitecture

    Unknown

  • Architecture and implementation of a VLIW supercomputer

    Robert P. Colwell;W. Eric Hall;Chandra S. Joshi;David B. Papworth

  • Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations

    Jeffrey M. Abramson;David B. Papworth;Haitham H. Akkary;Andrew F. Glew

  • Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state

    David B. Papworth;Michael A. Fetterman;Andrew F. Glew;Robert P. Colwell

  • Apparatus and method for handling string operations in a pipelined processor

    David B. Papworth;Michael A. Fetterman;Andrew F. Glew;Lawrence O. Smith

  • A VLIW architecture for a trace scheduling compiler

    Unknown

  • Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor

    David B. Papworth;Glenn J. Hinton

  • Method and apparatus for dynamic allocation of multiple buffers in a processor

    David B. Papworth;Andrew F. Glew;Glenn J. Hinton;Robert P. Colwell

  • Method and apparatus for performing error correction on data from an external memory

    John M. Bauer;Glenn J. Hinton;Gregory P. Meece;David B. Papworth

  • Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system

    Jeffrey M. Abramson;Haitham Akkary;Andrew F. Glew;Glenn J. Hinton

  • Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor

    Darrell D. Boggs;Robert P. Colwell;Michael A. Fetterman;Andrew F. Glew

Frequent Co-Authors

Glenn J. Hinton
Glenn J. Hinton Intel (United States)

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