2004 - ACM Fellow For inventions in processor architecture and design.
Stamatis Vassiliadis spends much of his time researching Parallel computing, Computer hardware, Field-programmable gate array, Instructions per cycle and Embedded system. Stamatis Vassiliadis regularly ties together related areas like Programming language in his Parallel computing studies. His study in Computer hardware is interdisciplinary in nature, drawing from both Value, Control unit, CMOS and Interlock.
His study in the field of Reconfigurable computing also crosses realms of Throughput and Clock rate. He has included themes like Instruction stream and Branch in his Instructions per cycle study. His work in Embedded system addresses subjects such as Microcode, which are connected to disciplines such as Scheme, Benchmark, JPEG and Microarchitecture.
His primary scientific interests are in Parallel computing, Embedded system, Computer hardware, Computer architecture and Field-programmable gate array. In his study, which falls under the umbrella issue of Parallel computing, Micro-operation is strongly linked to Instructions per cycle. His studies deal with areas such as Software and Compiler as well as Embedded system.
The concepts of his Computer hardware study are interwoven with issues in Scalability and Parallel processing. His Computer architecture study typically links adjacent topics like Microcode. His research in the fields of Virtex, Reconfigurable computing and VHDL overlaps with other disciplines such as Control reconfiguration and Throughput.
Stamatis Vassiliadis mainly investigates Parallel computing, Embedded system, Field-programmable gate array, Computer architecture and Speedup. His Parallel computing research incorporates themes from Overhead and Byte. His Embedded system research is multidisciplinary, incorporating elements of Network topology, Software, Compiler and Software-defined radio.
His Field-programmable gate array study improves the overall literature in Computer hardware. The Computer architecture study combines topics in areas such as Modeling and simulation and Design space exploration. His Speedup study integrates concerns from other disciplines, such as Algorithm, Hardware acceleration, Instruction set and MicroBlaze.
His primary areas of study are Parallel computing, Field-programmable gate array, Embedded system, Reconfigurable computing and SIMD. His study in Parallel computing is interdisciplinary in nature, drawing from both Byte and Data structure alignment. His Field-programmable gate array research entails a greater understanding of Computer hardware.
His Embedded system study incorporates themes from Multiplexing, Software, Compiler and Interconnection. He has researched Reconfigurable computing in several fields, including Logic synthesis, Hardware compatibility list and Pattern matching. The study incorporates disciplines such as Overhead, Parallel processing and MMX in addition to SIMD.
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The MOLEN polymorphic processor
S. Vassiliadis;S. Wong;G. Gaydadjiev;K. Bertels.
IEEE Transactions on Computers (2004)
64-bit floating-point FPGA matrix multiplication
Yong Dou;S. Vassiliadis;G. K. Kuzmanov;G. N. Gaydadjiev.
field programmable gate arrays (2005)
Parallel Computer Architecture
Silvia M. Müller;Per Stenström;Mateo Valero;Stamatis Vassiliadis.
european conference on parallel processing (2000)
Regular expression matching for reconfigurable packet inspection
Joao Bispo;Ioannis Sourdis;Joao M.P.Cardoso;Stamatis Vassiliadis.
field-programmable technology (2006)
Improving SHA-2 hardware implementations
Ricardo Chaves;Georgi Kuzmanov;Leonel Sousa;Stamatis Vassiliadis.
Lecture Notes in Computer Science (2006)
Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures
Eritsuku Maaku Shiyuwatsutsu;Sutemateizu Buashiriadesu.
(1987)
Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures
Eric M. Schwarz;Stamatis Vassiliadis.
(1987)
A load-instruction unit for pipelined processors
R. J. Eickemeyer;S. Vassiliadis.
Ibm Journal of Research and Development (1993)
The performance potential of data dependence speculation and collapsing
Yiannakis Sazeides;Stamatis Vassiliadis;James E. Smith.
international symposium on microarchitecture (1996)
Generalized 7/3 counters
Sutamateisu Bashiriadeisu;Eritsuku Maaku Shiyuwarutsu.
(1991)
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