2015 - ACM Distinguished Member
2009 - ACM Senior Member
Leonel Sousa mainly focuses on Parallel computing, Biochip, Spin valve, Embedded system and Throughput. The various areas that he examines in his Parallel computing study include Decoding methods, Low-density parity-check code, Very-large-scale integration and Cryptography. His studies in Biochip integrate themes in fields like Biosensor, Microsystem, Spectrum analyzer and Reading.
His Spin valve study is associated with Magnetoresistance. His Embedded system research is multidisciplinary, incorporating perspectives in Digital signal processing and Computer hardware. His biological study spans a wide range of topics, including Orders of magnitude and Sensitivity.
Leonel Sousa spends much of his time researching Parallel computing, Embedded system, Field-programmable gate array, Residue number system and Motion estimation. Leonel Sousa regularly links together related areas like Decoding methods in his Parallel computing studies. He has included themes like Scalability, Distributed computing, Cryptography, Encoder and Software in his Embedded system study.
His work deals with themes such as Computer architecture, Computation and Application-specific integrated circuit, which intersect with Field-programmable gate array. His Residue number system study incorporates themes from Converters, Modular arithmetic and Modulo. His Motion estimation research is multidisciplinary, incorporating elements of Pixel, Real-time computing, Estimator and Computer hardware.
The scientist’s investigation covers issues in Parallel computing, Residue number system, Arithmetic, Artificial intelligence and Cache. Leonel Sousa has researched Parallel computing in several fields, including Decoding methods, Frame rate and Kernel. His work carried out in the field of Residue number system brings together such families of science as Sign, Converters, Application-specific integrated circuit and Integer.
As a part of the same scientific family, Leonel Sousa mostly works in the field of Arithmetic, focusing on Modulo and, on occasion, Modular design. His research integrates issues of Instruction set and Speedup in his study of Multi-core processor. His research investigates the link between Energy consumption and topics such as Scheduling that cross with problems in Embedded system.
His main research concerns Arithmetic, Residue number system, Cache, Parallel computing and Modulo. His Arithmetic research focuses on subjects like Digital signal processing, which are linked to Electronic circuit. The study incorporates disciplines such as Application-specific integrated circuit, Integer and Product in addition to Residue number system.
His studies deal with areas such as Decoding methods, Frame rate, Frequency scaling and Random access as well as Parallel computing. His Modulo course of study focuses on Logic gate and Modular design, Low-power electronics and Computation. His Set study also includes fields such as
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Communication contention in task scheduling
O. Sinnen;L.A. Sousa.
IEEE Transactions on Parallel and Distributed Systems (2005)
Improving SHA-2 hardware implementations
Ricardo Chaves;Georgi Kuzmanov;Leonel Sousa;Stamatis Vassiliadis.
Lecture Notes in Computer Science (2006)
Cache-aware Roofline model: Upgrading the loft
Aleksandar Ilic;Frederico Pratas;Leonel Sousa.
IEEE Computer Architecture Letters (2014)
Massively LDPC Decoding on Multicore Architectures
G Falcao;L Sousa;V Silva.
IEEE Transactions on Parallel and Distributed Systems (2011)
General method for eliminating redundant computations in video coding
Electronics Letters (2000)
Femtomolar limit of detection with a magnetoresistive biochip.
V.C. Martins;F.A. Cardoso;J. Germano;S. Cardoso.
Biosensors and Bioelectronics (2009)
Toward a realistic task scheduling model
O. Sinnen;L.A. Sousa;F.E. Sandnes.
IEEE Transactions on Parallel and Distributed Systems (2006)
List scheduling: extension for contention awareness and evaluation of node priorities for heterogeneous cluster architectures ☆
Oliver Sinnen;Leonel Sousa.
parallel computing (2004)
A universal architecture for designing efficient modulo 2/sup n/+1 multipliers
L. Sousa;R. Chaves.
IEEE Transactions on Circuits and Systems I-regular Papers (2005)
A Survey on Fully Homomorphic Encryption: An Engineering Perspective
Paulo Martins;Leonel Sousa;Artur Mariano.
ACM Computing Surveys (2017)
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