World's Best Scientists 2026 revealed!

D-Index & Metrics

Computer Science

D-Index
41
Citations
8453
World Ranking
8732
National Ranking
160

Electronics and Electrical Engineering

D-Index
39
Citations
8113
World Ranking
4613
National Ranking
74

Overview

Paolo Ienne is affiliated with the École Polytechnique Fédérale de Lausanne in Switzerland. Their research contributions are primarily focused on the field of Computer Science, with a notable emphasis on several subfields including Hardware and Architecture, Computer Networks and Communications, Electrical and Electronic Engineering, Computational Theory and Mathematics, and Computer Vision and Pattern Recognition.

Their main topics of work include Embedded Systems Design Techniques, Parallel Computing and Optimization Techniques, Interconnection Networks and Systems, Graph Theory and Algorithms, VLSI and Analog Circuit Testing, Data Management and Algorithms, and VLSI and FPGA Design Techniques.

Paolo Ienne has co-authored multiple papers with frequent collaborators such as Lana Josipović, Andrea Guerrieri, Jovan Blanuša, Kubilay Atasu, and Mikhail Asiatici.

Prominent recent papers by Paolo Ienne include:

  • Synthesizing General-Purpose Code Into Dynamically Scheduled Circuits, 2021, IEEE Circuits and Systems Magazine
  • From C/C++ Code to High-Performance Dataflow Circuits, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Manycore clique enumeration with fast set intersections, 2020, Proceedings of the VLDB Endowment
  • DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles, 2023, ACM Transactions on Parallel Computing

The scientist has been regularly publishing in venues such as ACM Transactions on Reconfigurable Technology and Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, arXiv (Cornell University), IEEE Circuits and Systems Magazine, and Proceedings of the VLDB Endowment.

Best Publications

  • ShiDianNao: shifting vision processing closer to the sensor

    Zidong Du;Robert Fasthuber;Tianshi Chen;Paolo Ienne

  • Automatic application-specific instruction-set extensions under microarchitectural constraints

    Kubilay Atasu;Laura Pozzi;Paolo Ienne

  • Mobile Robot Miniaturisation: A Tool for Investigation in Control Algorithms

    Francesco Mondada;Edoardo Franzi;Paolo Ienne

  • Variable latency speculative addition: a new paradigm for arithmetic circuit design

    Ajay K. Verma;Philip Brisk;Paolo Ienne

  • Exact and approximate algorithms for the extension of embedded processor instruction sets

    L. Pozzi;K. Atasu;P. Ienne

  • Customizable Embedded Processors: Design Technologies and Applications

    Paolo Ienne;Rainer Leupers

  • Seamless hardware-software integration in reconfigurable computing systems

    M. Vuletid;L. Pozzi;P. Ienne

  • Wear unleveling: improving NAND flash lifetime by balancing page endurance

    Xavier Jimenez;David Novo;Paolo Ienne

  • An adaptive low-power transmission scheme for on-chip networks

    F. Worm;P. Ienne;P. Thiran;G. de micheli

  • Exploiting pipelining to relax register-file port constraints of instruction-set extensions

    Laura Pozzi;Paolo Ienne

  • A first step towards automatic application of power analysis countermeasures

    Ali Galip Bayrak;Francesco Regazzoni;Philip Brisk;Francois-Xavier Standaert

  • Automatic instruction set extension and utilization for embedded processors

    A. Peymandoust;L. Pozzi;P. Ienne;G. De Micheli

  • Dynamically Scheduled High-level Synthesis

    Lana Josipović;Radhika Ghosal;Paolo Ienne

  • A robust self-calibrating transmission scheme for on-chip networks

    F. Worm;P. Ienne;P. Thiran;G. De Micheli

  • Sleuth: automated verification of software power analysis countermeasures

    Ali Galip Bayrak;Francesco Regazzoni;David Novo;Paolo Ienne

  • High performance comparison-based sorting algorithm on many-core GPUs

    Xiaochun Ye;Dongrui Fan;Wei Lin;Nan Yuan

  • Introduction of local memory elements in instruction set extensions

    Partha Biswas;Vinay Choudhary;Kubilay Atasu;Laura Pozzi

  • Hardware system synthesis from Domain-Specific Languages

    Nithin George;HyoukJoong Lee;David Novo;Tiark Rompf

  • Elastic CGRAs

    Yuanjie Huang;Paolo Ienne;Olivier Temam;Yunji Chen

  • Efficient synthesis of compressor trees on FPGAs

    Hadi Parandeh-Afshar;Philip Brisk;Paolo Ienne

  • A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions

    Francesco Regazzoni;Alessandro Cevrero;François-Xavier Standaert;Stephane Badel

Frequent Co-Authors

Philip Brisk
Philip Brisk University of California, Riverside
Yusuf Leblebici
Yusuf Leblebici École Polytechnique Fédérale de Lausanne
Francesco Regazzoni
Francesco Regazzoni Polytechnic University of Milan
Patrick Thiran
Patrick Thiran École Polytechnique Fédérale de Lausanne
Nikil Dutt
Nikil Dutt University of California, Irvine
Edoardo Charbon
Edoardo Charbon École Polytechnique Fédérale de Lausanne
Alan Mishchenko
Alan Mishchenko University of California, Berkeley
Christof Paar
Christof Paar Max Planck Institute for Security and Privacy
Olivier Temam
Olivier Temam DeepMind (United Kingdom)
Andreas Burg
Andreas Burg École Polytechnique Fédérale de Lausanne

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