His primary areas of study are Embedded system, Parallel computing, Instruction set, Speedup and System on a chip. His biological study spans a wide range of topics, including Process, Computer hardware, Artificial neural network, Side channel attack and Programming paradigm. His Parallel computing research includes elements of Arithmetic circuit complexity, Logic synthesis, Heuristic, Arithmetic and Sorting algorithm.
His study in Instruction set is interdisciplinary in nature, drawing from both Application-specific integrated circuit, State, Application software, Advanced Encryption Standard and CMOS. His work deals with themes such as Algorithm and Cache, which intersect with Speedup. The concepts of his System on a chip study are interwoven with issues in Programming language, Electronic engineering, Chip and Robustness.
The scientist’s investigation covers issues in Embedded system, Field-programmable gate array, Parallel computing, Instruction set and Logic synthesis. His work in Embedded system covers topics such as Virtual memory which are related to areas like Coprocessor. Paolo Ienne focuses mostly in the field of Field-programmable gate array, narrowing it down to topics relating to Computer engineering and, in certain cases, Set and Artificial neural network.
His Parallel computing research is multidisciplinary, relying on both Overhead and Heuristic. His work on Computer architecture expands to the thematically related Instruction set. His Logic synthesis study incorporates themes from Electronic circuit and Arithmetic.
His main research concerns Field-programmable gate array, Embedded system, Parallel computing, High-level synthesis and Computer engineering. Paolo Ienne combines subjects such as Lookup table, Structure, Design space exploration and Solid modeling with his study of Field-programmable gate array. His Embedded system research incorporates themes from Execution model, Software, Cloud computing and Instruction set.
His studies in Parallel computing integrate themes in fields like Job scheduler, Scalability, Thread and Central processing unit. His High-level synthesis research is multidisciplinary, incorporating perspectives in Forward error correction, Electronic circuit, Dataflow and Dynamic priority scheduling. His Computer engineering research is multidisciplinary, incorporating elements of Routing, Set and Interconnection.
His primary areas of investigation include Embedded system, Field-programmable gate array, Logic synthesis, Computer engineering and Algorithm. Paolo Ienne works on Embedded system which deals in particular with High-level synthesis. As part of one scientific family, he deals mainly with the area of Field-programmable gate array, narrowing it down to issues related to the Electronic circuit, and often Scheduling, Very long instruction word, Compiler and Granularity.
His Logic synthesis study combines topics in areas such as Toolchain, Key and Speedup. The various areas that Paolo Ienne examines in his Computer engineering study include Dram, Transistor, CMOS and Set. His research in Efficient energy use intersects with topics in Artificial neural network, Random access memory, Static random-access memory, Memory footprint and Convolutional neural network.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
ShiDianNao: shifting vision processing closer to the sensor
Zidong Du;Robert Fasthuber;Tianshi Chen;Paolo Ienne.
international symposium on computer architecture (2015)
Mobile Robot Miniaturisation: A Tool for Investigation in Control Algorithms
Francesco Mondada;Edoardo Franzi;Paolo Ienne.
international symposium on experimental robotics (1993)
Automatic application-specific instruction-set extensions under microarchitectural constraints
Kubilay Atasu;Laura Pozzi;Paolo Ienne.
International Journal of Parallel Programming (2003)
Variable latency speculative addition: a new paradigm for arithmetic circuit design
Ajay K. Verma;Philip Brisk;Paolo Ienne.
design, automation, and test in europe (2008)
Exact and approximate algorithms for the extension of embedded processor instruction sets
L. Pozzi;K. Atasu;P. Ienne.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2006)
Customizable Embedded Processors: Design Technologies and Applications
Paolo Ienne;Rainer Leupers.
Seamless hardware-software integration in reconfigurable computing systems
M. Vuletid;L. Pozzi;P. Ienne.
IEEE Design & Test of Computers (2005)
An adaptive low-power transmission scheme for on-chip networks
F. Worm;P. Ienne;P. Thiran;G. de micheli.
international symposium on systems synthesis (2002)
Wear unleveling: improving NAND flash lifetime by balancing page endurance
Xavier Jimenez;David Novo;Paolo Ienne.
file and storage technologies (2014)
Exploiting pipelining to relax register-file port constraints of instruction-set extensions
Laura Pozzi;Paolo Ienne.
compilers, architecture, and synthesis for embedded systems (2005)
Profile was last updated on December 6th, 2021.
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