World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
51
Citations
10682
World Ranking
2657
National Ranking
1011

Research.com Recognitions

  • 2013 - IEEE Fellow For contributions to packaging for high performance computing systems

Overview

What is he best known for?

The fields of study he is best known for:

  • Electrical engineering
  • Operating system
  • Central processing unit

Paul W. Coteus mainly focuses on Massively parallel, Integrated circuit, Supercomputer, Electrical engineering and Electronic engineering. The Massively parallel study combines topics in areas such as IBM, Blue gene and Node. Paul W. Coteus interconnects Integrated circuit design, Structure, Layer and Interconnection in the investigation of issues within Integrated circuit.

His work deals with themes such as Software, Application-specific integrated circuit and Network packet, which intersect with Supercomputer. He has researched Electrical engineering in several fields, including Interface, Smart memory and Offset. His Electronic engineering research is multidisciplinary, relying on both Busbar, Interleaved memory, Electric power transmission and Inductive coupling.

His most cited work include:

  • Multi-petascale highly efficient parallel supercomputer (385 citations)
  • Overview of the Blue Gene/L system architecture (370 citations)
  • When are transmission-line effects important for on-chip interconnections? (353 citations)

What are the main themes of his work throughout his whole career to date?

His primary areas of study are Electrical engineering, Computer hardware, Electronic engineering, Optoelectronics and Chip. Paul W. Coteus studied Electrical engineering and Interposer that intersect with Transverse plane and Plane. In most of his Computer hardware studies, his work intersects topics such as Embedded system.

His studies examine the connections between Electronic engineering and genetics, as well as such issues in Integrated circuit, with regards to Supercomputer. His Optoelectronics research includes themes of Layer and Substrate. His study in Chip is interdisciplinary in nature, drawing from both Mechanical engineering, Electrical conductor and Lead frame.

He most often published in these fields:

  • Electrical engineering (27.49%)
  • Computer hardware (24.70%)
  • Electronic engineering (20.32%)

What were the highlights of his more recent work (between 2014-2020)?

  • Electrical engineering (27.49%)
  • Inductor (1.99%)
  • Printed circuit board (6.37%)

In recent papers he was focusing on the following fields of study:

The scientist’s investigation covers issues in Electrical engineering, Inductor, Printed circuit board, Electronic engineering and Memory module. Paul W. Coteus applies his multidisciplinary studies on Electrical engineering and Anode in his research. His Inductor research incorporates elements of Planar, Transformer, Sense and Inductance.

His research integrates issues of Electrical contacts, Substrate, Topology and Electrical conductor in his study of Printed circuit board. The concepts of his Electronic engineering study are interwoven with issues in Network link, Computer network, Network packet and Power mode. Memory module is a subfield of Computer hardware that Paul W. Coteus studies.

Between 2014 and 2020, his most popular works were:

  • Flexible cold plate with enhanced flexibility (17 citations)
  • Analytic model for power MOSFET turn-off switching loss under the effect of significant current diversion at fast switching events (8 citations)
  • Power management of network links (6 citations)

In his most recent research, the most cited papers focused on:

  • Electrical engineering
  • Operating system
  • Central processing unit

His primary areas of study are Current, Control theory, Electronic engineering, MOSFET and Composite material. The various areas that Paul W. Coteus examines in his Control theory study include Clock skew, Clock domain crossing, Synchronous circuit, Phase and Quadrature. Paul W. Coteus has researched Electronic engineering in several fields, including Network link, Computer network, Network packet, Power mode and Power management.

His Composite material research includes themes of Electronic component, Planar and Structural engineering. His work carried out in the field of Structural engineering brings together such families of science as Conductive materials, Flexibility and Heat sink. Capacitor is a subfield of Electrical engineering that Paul W. Coteus tackles.

Best Publications

  • Massively parallel supercomputer

    Matthias A. Blumrich;Dong Chen;George L. Chiu;Thomas M. Cipolla

  • An Overview of the BlueGene/L Supercomputer

    N.R. Adiga;G. Almasi;G.S. Almasi;Y. Aridor

  • Overview of the Blue Gene/L system architecture

    A. Gara;M. A. Blumrich;D. Chen;G. L.-T. Chiu

  • When are transmission-line effects important for on-chip interconnections?

    A. Deutsch;G.V. Kopcsay;P.J. Restle;H.H. Smith

  • Multi-petascale highly efficient parallel supercomputer

    Sameh Asaad;Ralph E. Bellofatto;Michael A. Blocksome;Matthias A. Blumrich

  • RFID integrated in electronic assets

    Michael John Brady;Paul W. Coteus;Dah-Weih Duan;Venkata S. R. Kodukula

  • On-chip wiring design challenges for gigahertz operation

    A. Deutsch;P.W. Coteus;G.V. Kopcsay;H.H. Smith

  • Ultrascalable petaflop parallel supercomputer

    Matthias A. Blumrich;Dong Chen;George Chiu;Thomas M. Cipolla

  • Practical Strategies for Power-Efficient Computing Technologies

    L. Chang;D.J. Frank;R.K. Montoye;S.J. Koester

  • DOE Advanced Scientific Computing Advisory Subcommittee (ASCAC) Report: Top Ten Exascale Research Challenges

    Robert Lucas;James Ang;Keren Bergman;Shekhar Borkar

  • Method and apparatus for cooling an equipment enclosure through closed-loop liquid-assisted air cooling in combination with direct liquid cooling

    Shawn A. Hall;Shurong Tian;Paul W. Coteus;John P. Karidis

  • System and method for inspection and alignment of semiconductor chips and conductive lead frames

    Thomas M. Cipolla;Paul W. Coteus;Glen W. Johnson;Philip Murphy

  • Smart memory interface

    Paul William Coteus;Daniel Mark Dreps;Frank Ferraiolo

  • 3-dimensional integrated circuit architecture, structure and method for fabrication thereof

    Kerry Bernstein;Paul W. Coteus;Philip G. Emma

  • Structure comprising 3-dimensional integrated circuit architecture, circuit structure, and instructions for fabrication thereof

    Kerry Bernstein;Paul William Coteus;Philip George Emma

  • Lead frame package for electronic devices

    Thomas Mario Cipolla;Paul William Coteus

  • Method and apparatus of water cooling several parallel circuit cards each containing several chip packages

    Thomas M. Cipolla;Shurong Tian;Evan George Colgan;Paul W. Coteus

  • Enhanced cascade interconnected memory system

    Kevin C. Gower;Paul W. Coteus;Warren E. Maule;Robert B. Tremaine

  • Advanced memory device having improved performance, reduced power and increased reliability

    Kyu-hyoun Kim;George L. Chiu;Paul W. Coteus;Daniel M. Dreps

  • When are transmission-line effects important for on-chip interconnections

    A. Deutsch;G.V. Kopcsay;P. Restle;G. Katopis

Frequent Co-Authors

Kevin C. Gower
Kevin C. Gower IBM (United States)
Robert H. Dennard
Robert H. Dennard IBM (United States)
Phillip J. Restle
Phillip J. Restle IBM (United States)
Daniel J. Friedman
Daniel J. Friedman IBM (United States)
Leland Chang
Leland Chang IBM Research - Thomas J. Watson Research Center
Keith A. Jenkins
Keith A. Jenkins IBM (United States)
Steven J. Koester
Steven J. Koester University of Minnesota
David J. Frank
David J. Frank IBM (United States)

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