World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
48
Citations
14708
World Ranking
3014
National Ranking
1131

Research.com Recognitions

  • 2003 - IEEE Fellow For contributions to solid-state devices and ultra-small CMOS devices.

Overview

What is he best known for?

The fields of study he is best known for:

  • Quantum mechanics
  • Semiconductor
  • Electron

David J. Frank mainly focuses on CMOS, Electronic engineering, Electrical engineering, Optoelectronics and MOSFET. His studies deal with areas such as Power, Carbon nanotube, Quantum tunnelling and Leakage as well as CMOS. David J. Frank works in the field of Electronic engineering, namely Static random-access memory.

His Electrical engineering study combines topics in areas such as Power consumption, Low-power electronics, Silicon on insulator and Technology forecasting. His biological study spans a wide range of topics, including Electron and Quasi one dimensional. The various areas that David J. Frank examines in his MOSFET study include Threshold voltage, Condensed matter physics and Gate oxide.

His most cited work include:

  • Device scaling limits of Si MOSFETs and their application dependencies (1082 citations)
  • CMOS scaling into the nanometer regime (724 citations)
  • Three-dimensional integrated circuits (636 citations)

What are the main themes of his work throughout his whole career to date?

His scientific interests lie mostly in Optoelectronics, Electrical engineering, Electronic engineering, CMOS and MOSFET. His research integrates issues of Layer and Transistor, Voltage in his study of Optoelectronics. His research investigates the link between Electrical engineering and topics such as Silicon on insulator that cross with problems in Integrated circuit, Copper interconnect and Gate oxide.

His Electronic engineering study combines topics from a wide range of disciplines, such as Power, Cmos scaling, Electronic circuit and Dissipation. His studies in CMOS integrate themes in fields like Quantum tunnelling, Low-power electronics and Engineering physics. His MOSFET research is multidisciplinary, incorporating elements of Silicon and Dopant.

He most often published in these fields:

  • Optoelectronics (43.17%)
  • Electrical engineering (38.85%)
  • Electronic engineering (29.50%)

What were the highlights of his more recent work (between 2012-2020)?

  • Optoelectronics (43.17%)
  • Electrical engineering (38.85%)
  • Silicon (8.63%)

In recent papers he was focusing on the following fields of study:

David J. Frank mostly deals with Optoelectronics, Electrical engineering, Silicon, Ferroelectricity and Electronic engineering. David J. Frank has included themes like Layer, Substrate, Capacitance and MOSFET in his Optoelectronics study. His Capacitance research includes themes of Subthreshold conduction and Transistor.

His research in Electrical engineering is mostly focused on Semiconductor. In his work, Electrode, Nanoscopic scale and Characterization is strongly intertwined with Epitaxy, which is a subfield of Silicon. The concepts of his Electronic engineering study are interwoven with issues in Microprocessor, Silicon on insulator and Low voltage, Voltage.

Between 2012 and 2020, his most popular works were:

  • Toward High-Performance Digital Logic Technology With Carbon Nanotubes (179 citations)
  • Switching of ferroelectric polarization in epitaxial BaTiO3 films on silicon without a conducting bottom electrode (152 citations)
  • The Quantum Metal Ferroelectric Field-Effect Transistor (43 citations)

In his most recent research, the most cited papers focused on:

  • Quantum mechanics
  • Semiconductor
  • Electron

David J. Frank focuses on Optoelectronics, Nanotechnology, Density scaling, Disruptive innovation and Ballistic conduction. In general Optoelectronics study, his work on Ferroelectricity often relates to the realm of Scanning transmission electron microscopy, thereby connecting several areas of interest. Nanotechnology and CMOS are commonly linked in his work.

Best Publications

  • Device scaling limits of Si MOSFETs and their application dependencies

    D.J. Frank;R.H. Dennard;E. Nowak;P.M. Solomon

  • CMOS scaling into the nanometer regime

    Yuan Taur;D.A. Buchanan;Wei Chen;D.J. Frank

  • Three-dimensional integrated circuits

    A. W. Topol;D. C. La Tulipe;L. Shi;D. J. Frank

  • High-performance CMOS variability in the 65-nm regime and beyond

    K. Bernstein;D. J. Frank;A. E. Gattiker;W. Haensch

  • Nanoscale CMOS

    H.-S.P. Wong;D.J. Frank;P.M. Solomon;C.H.J. Wann

  • Quasi-one-dimensional electron states in a split-gate GaAs/AlGaAs heterostructure

    S.E. Laux;D.J. Frank;Frank Stern

  • Monte Carlo modeling of threshold variation due to dopant fluctuations

    D.J. Frank;Y. Taur;M. Ieong;H.-S.P. Wong

  • Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation

    H.-S.P. Wong;D.J. Frank;P.M. Solomon

  • Generalized scale length for two-dimensional effects in MOSFETs

    D.J. Frank;Y. Taur;H.-S.P. Wong

  • 25 nm CMOS design considerations

    Y. Taur;C.H. Wann;D.J. Frank

  • Power-constrained CMOS scaling limits

    D. J. Frank

  • Toward High-Performance Digital Logic Technology With Carbon Nanotubes

    George S. Tulevski;Aaron D. Franklin;David Frank;Jose M. Lobez

  • Highly efficient algorithm for percolative transport studies in two dimensions.

    D.J. Frank;C.J. Lobb

  • Switching of ferroelectric polarization in epitaxial BaTiO3 films on silicon without a conducting bottom electrode

    Catherine Dubourdieu;John Bruley;Thomas M. Arruda;Agham Posadas

  • Empirical fit to band discontinuities and barrier heights in III–V alloy systems

    Sandip Tiwari;David J. Frank

  • Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)

    A.W. Topol;D.C. La Tulipe;L. Shi;S.M. Alam

  • New phenomena in coupled transport between 2D and 3D electron-gas layers.

    P. M. Solomon;P. J. Price;D. J. Frank;D. C. La Tulipe

  • Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication

    K.W. Guarini;A.W. Topol;M. Ieong;R. Yu

  • Practical Strategies for Power-Efficient Computing Technologies

    L. Chang;D.J. Frank;R.K. Montoye;S.J. Koester

  • Monte Carlo analysis of semiconductor devices: the DAMOCLES program

    S. E. Laux;M. V. Fischetti;D. J. Frank

Frequent Co-Authors

Paul M. Solomon
Paul M. Solomon IBM (United States)
Yuan Taur
Yuan Taur University of California, San Diego
Wilfried Haensch
Wilfried Haensch Argonne National Laboratory
Leland Chang
Leland Chang IBM Research - Thomas J. Watson Research Center
Sandip Tiwari
Sandip Tiwari Cornell University
Meikei Ieong
Meikei Ieong Simbury Limited
Guy M. Cohen
Guy M. Cohen IBM (United States)
Vijay Narayanan
Vijay Narayanan IBM (United States)
Thomas N. Jackson
Thomas N. Jackson Pennsylvania State University
James H. Stathis
James H. Stathis IBM (United States)

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