World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
66
Citations
22667
World Ranking
1121
National Ranking
469

Materials Science

D-Index
65
Citations
22269
World Ranking
5509
National Ranking
1430

Overview

Yuan Taur is affiliated with the University of California, San Diego in the United States. Their research primarily focuses on advances in semiconductor devices and circuit design, with a notable emphasis on silicon carbide semiconductor technologies and related semiconductor materials and devices. The work spans fields of engineering, particularly electrical and electronic engineering.

Their publication record includes research articles, book contributions, and collaborations across various venues and topics. Yuan Taur is associated with several frequent co-authors including T.H. Ning, Marlene James, Narain Arora Silterra, Inc Jagadish, and Santosh Kurinec.

Frequent publication venues for Yuan Taur include:

  • IEEE Journal of Photovoltaics
  • IEEE Transactions on Electron Devices
  • Solid-State Electronics
  • Microelectronic Engineering
  • Cambridge University Press eBooks

Among their recent papers are:

  • On the Log-Linear Inversion-Charge Relation for MOSFET Modeling, 2021, IEEE Transactions on Electron Devices
  • Effects of BOX thickness, silicon thickness, and backgate bias on SCE of ET-SOI MOSFETs, 2021, Microelectronic Engineering
  • Non-GCA modeling of near threshold I-V characteristics of DG MOSFETs, 2020, Solid-State Electronics
  • IEEE Journal of Photovoltaics, 2021, IEEE Journal of Photovoltaics
  • A non-GCA model for ground-plane MOSFETs, 2023, Solid-State Electronics

Yuan Taur also contributed to the book "Fundamentals of Modern VLSI Devices," published by Cambridge University Press in 2021.

Their work covers topics such as:

  • Advancements in Semiconductor Devices and Circuit Design
  • Silicon Carbide Semiconductor Technologies
  • Semiconductor materials and devices
  • Integrated Circuits and Semiconductor Failure Analysis
  • Low-power high-performance VLSI design

Best Publications

  • Fundamentals of Modern VLSI Devices

    Yuan Taur;Tak H. Ning

  • Device scaling limits of Si MOSFETs and their application dependencies

    D.J. Frank;R.H. Dennard;E. Nowak;P.M. Solomon

  • CMOS scaling into the nanometer regime

    Yuan Taur;D.A. Buchanan;Wei Chen;D.J. Frank

  • Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's

    S.-H. Lo;D.A. Buchanan;Y. Taur;W. Wang

  • CMOS design near the limit of scaling

    Y. Taur

  • A continuous, analytic drain-current model for DG MOSFETs

    Yuan Taur;Xiaoping Liang;Wei Wang;Huaxin Lu

  • Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs

    Y. Taur

  • Monte Carlo modeling of threshold variation due to dopant fluctuations

    D.J. Frank;Y. Taur;M. Ieong;H.-S.P. Wong

  • An analytical solution to a double-gate MOSFET with undoped body

    Yuan Taur

  • Generalized scale length for two-dimensional effects in MOSFETs

    D.J. Frank;Y. Taur;H.-S.P. Wong

  • Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel

    H.-S.P. Wong;K.K. Chan;Y. Taur

  • A 2-D analytical solution for SCEs in DG MOSFETs

    Xiaoping Liang;Yuan Taur

  • 25 nm CMOS design considerations

    Y. Taur;C.H. Wann;D.J. Frank

  • Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 /spl mu/m MOSFET's

    Hon-Sum Wong;Yuan Taur

  • SOI CMOS structure

    Wei Chen;Devendra Kumar Sadana;Yuan Taur

  • Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides

    S.-H. Lo;D. A. Buchanan;Y. Taur

  • A new 'shift and ratio' method for MOSFET channel-length extraction

    Y. Taur;D.S. Zicherman;D.R. Lombardi;P.J. Restle

  • An analytic potential model for symmetric and asymmetric DG MOSFETs

    Huaxin Lu;Yuan Taur

  • CMOS devices below 0.1 /spl mu/m: how high will performance go?

    Yuan Taur;E.J. Nowak

  • Explicit Continuous Models for Double-Gate and Surrounding-Gate MOSFETs

    Bo Yu;Huaxin Lu;Minjian Liu;Yuan Taur

Frequent Co-Authors

Peter M. Asbeck
Peter M. Asbeck University of California, San Diego
David J. Frank
David J. Frank IBM (United States)
Paul C. McIntyre
Paul C. McIntyre Stanford University
Keith A. Jenkins
Keith A. Jenkins IBM (United States)
Sorin Cristoloveanu
Sorin Cristoloveanu Grenoble Institute of Technology
Tak H. Ning
Tak H. Ning IBM (United States)
Clement Hsingjen Wann
Clement Hsingjen Wann Taiwan Semiconductor Manufacturing Company (Taiwan)
Hanping Chen
Hanping Chen Huazhong University of Science and Technology
Robert H. Dennard
Robert H. Dennard IBM (United States)
Mark J. W. Rodwell
Mark J. W. Rodwell University of California, Santa Barbara

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