University of Michigan–Ann Arbor
Marios C. Papaefthymiou focuses on Electronic engineering, Low-power electronics, CMOS, Integrated circuit design and Adiabatic circuit. His Logic gate study in the realm of Electronic engineering interacts with subjects such as Dissipation and Boundary value problem. His biological study deals with issues like Pass transistor logic, which deal with fields such as Logic level, Precomputation and Cycles per instruction.
His Low-power electronics course of study focuses on Logic simulation and Topology, Quantization and Digital signal processing. His CMOS research is multidisciplinary, incorporating perspectives in Very-large-scale integration, Logic family and Power gating. His research integrates issues of Low voltage and Structure in his study of Integrated circuit design.
Marios C. Papaefthymiou mainly investigates Electronic engineering, Clock skew, CMOS, Low-power electronics and Clock gating. Electronic engineering and Electrical engineering are commonly linked in his work. In general Clock skew, his work in Timing failure is often linked to Retiming and Linear programming linking many areas of study.
His CMOS study combines topics from a wide range of disciplines, such as Adiabatic circuit, Logic family, Inductor, Logic gate and Very-large-scale integration. The various areas that Marios C. Papaefthymiou examines in his Low-power electronics study include Integrated circuit design and Logic synthesis. His Clock gating research includes elements of Clock network and Underclocking.
The scientist’s investigation covers issues in Electronic engineering, CPU multiplier, Clock gating, Digital clock manager and Underclocking. His Electronic engineering study which covers Inductor that intersects with Figure of merit. His research on Digital clock manager concerns the broader Clock skew.
Marios C. Papaefthymiou interconnects Synchronous circuit and Master clock in the investigation of issues within Clock skew. Marios C. Papaefthymiou studied Logic gate and Pass transistor logic that intersect with State. His CMOS study combines topics in areas such as Power consumption and Embedded system.
His primary scientific interests are in Simulation, Electronic engineering, Throughput, Chip and Sprint. In his research on the topic of Electronic engineering, Figure of merit is strongly related with Microprocessor. His work deals with themes such as Computation and Voltage, which intersect with Chip.
His study in Dark silicon is interdisciplinary in nature, drawing from both Single-core and Response time. His Mobile computing research is multidisciplinary, relying on both Real-time computing, Distributed computing and Mobile device. His Low-power electronics research integrates issues from NMOS logic, Logic gate, Logic family, Integrated circuit and Subthreshold conduction.
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Precomputation-based sequential logic optimization for low power
M. Alidina;J. Monteiro;S. Devadas;A. Ghosh.
IEEE Transactions on Very Large Scale Integration Systems (1994)
Arun Raghavan;Yixin Luo;Anuj Chandawalla;Marios Papaefthymiou.
high performance computer architecture (2012)
True single-phase adiabatic circuitry
Suhwan Kim;Marios C. Papaefthymiou.
IEEE Transactions on Very Large Scale Integration Systems (2001)
A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs
Suhwan Kim;S.V. Kosonocky;D.R. Knebel;K. Stawiasz.
IEEE Transactions on Circuits and Systems Ii-express Briefs (2007)
Energy-Efficient GHz-Class Charge-Recovery Logic
V.S. Sathe;J.-Y. Chueh;M.C. Papaefthymiou.
international solid state circuits conference (2007)
Resonant clock design for a power-efficient high-volume x86–64 microprocessor
V. S. Sathe;S. Arekapudi;A. Ishii;C. Ouyang.
international solid-state circuits conference (2012)
Optimizing two-phase, level-clocked circuitry
Alexander T. Ishii;Charles E. Leiserson;Marios C. Papaefthymiou.
Journal of the ACM (1997)
Charge-recovery computing on silicon
Suhwan Kim;C.H. Ziesler;M.C. Papaefthymiou.
IEEE Transactions on Computers (2005)
Block-based multiperiod dynamic memory design for low data-retention power
Joohee Kim;M.C. Papaefthymiou.
IEEE Transactions on Very Large Scale Integration Systems (2003)
Understanding retiming through maximum average-weight cycles
Marios C. Papaefthymiou.
acm symposium on parallel algorithms and architectures (1991)
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