D-Index & Metrics Best Publications
Anirudh Devgan

Anirudh Devgan

Synopsys (United States)
United States

Overview

What is he best known for?

The fields of study he is best known for:

  • Electrical engineering
  • Integrated circuit
  • Voltage

Anirudh Devgan mainly investigates Electronic engineering, Elmore delay, Integrated circuit design, Delay calculation and Dynamic logic. Anirudh Devgan interconnects Equivalent series inductance, Chip, Leakage, Integrated circuit and Topology in the investigation of issues within Electronic engineering. His work in Integrated circuit covers topics such as Noise margin which are related to areas like Static timing analysis.

Anirudh Devgan works mostly in the field of Elmore delay, limiting it down to concerns involving Routing and, occasionally, AND gate, Lumped capacitance model, Metric, Floorplan and Impulse response. His Integrated circuit design study frequently draws connections to adjacent fields such as RC time constant. His Delay calculation research is multidisciplinary, incorporating elements of Bottleneck, Integrated circuit layout, Application-specific integrated circuit and Propagation delay.

His most cited work include:

  • Full chip leakage-estimation considering power supply and temperature variations (254 citations)
  • Block-based Static Timing Analysis with Uncertainty (240 citations)
  • Wire segmenting for improved buffer insertion (207 citations)

What are the main themes of his work throughout his whole career to date?

His primary areas of investigation include Electronic engineering, Integrated circuit, Integrated circuit design, Electronic circuit and Leakage. His research integrates issues of Topology, Elmore delay and Voltage in his study of Electronic engineering. He combines subjects such as RC circuit, Routing, Dynamic logic and Logic gate with his study of Elmore delay.

His research investigates the connection between Integrated circuit and topics such as Circuit extraction that intersect with problems in Voltage drop. As part of the same scientific family, Anirudh Devgan usually focuses on Electronic circuit, concentrating on Transistor and intersecting with Power factor. In his study, Scaling is strongly linked to Chip, which falls under the umbrella field of Leakage.

He most often published in these fields:

  • Electronic engineering (63.04%)
  • Integrated circuit (19.57%)
  • Integrated circuit design (17.39%)

What were the highlights of his more recent work (between 2005-2009)?

  • Electronic engineering (63.04%)
  • Memory cell (6.52%)
  • Static random-access memory (6.52%)

In recent papers he was focusing on the following fields of study:

His primary areas of study are Electronic engineering, Memory cell, Static random-access memory, Electronic circuit and Lithography. His research on Electronic engineering often connects related areas such as Leakage. His Electronic circuit research includes elements of Die and Physical design.

His studies deal with areas such as Hybrid computer, Integrated circuit layout and Electronic design automation as well as Digital electronics. His work on Inverter and Ring oscillator as part of general Voltage study is frequently connected to Asymmetry, Pierce oscillator and Hartley oscillator, therefore bridging the gap between diverse disciplines of science and establishing a new relationship between them. In his research on the topic of Subthreshold conduction, Integrated circuit design is strongly related with AND gate.

Between 2005 and 2009, his most popular works were:

  • Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions (58 citations)
  • Analytical yield prediction considering leakage/performance correlation (28 citations)
  • Ring oscillator row circuit for evaluating memory cell performance (23 citations)

In his most recent research, the most cited papers focused on:

  • Electrical engineering
  • Integrated circuit
  • Geometry

His primary scientific interests are in Mathematical optimization, Parametric statistics, Static random-access memory, Memory cell and Subthreshold conduction. His Mathematical optimization research incorporates elements of Algorithm design, Design for manufacturability and Integrated circuit. His Static random-access memory study integrates concerns from other disciplines, such as Topology and Ring oscillator, Voltage.

The various areas that Anirudh Devgan examines in his Subthreshold conduction study include Linear programming, Electronic circuit, Speedup and Power gating. Anirudh Devgan conducted interdisciplinary study in his works that combined Hartley oscillator and Electronic engineering. The Electronic engineering study combines topics in areas such as Chip and Leakage.

This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.

Best Publications

Buffer insertion for noise and delay optimization

C.J. Alpert;A. Devgan;S.T. Quay.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1999)

476 Citations

Block-based Static Timing Analysis with Uncertainty

Anirudh Devgan;Chandramouli Kashyap.
international conference on computer aided design (2003)

357 Citations

Full chip leakage-estimation considering power supply and temperature variations

Haihua Su;Frank Liu;Anirudh Devgan;Emrah Acar.
international symposium on low power electronics and design (2003)

352 Citations

Wire segmenting for improved buffer insertion

Charles Alpert;Anirudh Devgan.
design automation conference (1997)

288 Citations

Efficient coupled noise estimation for on-chip interconnects

Anirudh Devgan.
international conference on computer aided design (1997)

243 Citations

How to efficiently capture on-chip inductance effects: introducing a new circuit element K

Anirudh Devgan;Hao Ji;Wayne Dai.
international conference on computer aided design (2000)

223 Citations

An efficient algorithm for statistical minimization of total power under timing yield constraints

Murari Mani;Anirudh Devgan;Michael Orshansky.
design automation conference (2005)

181 Citations

Parametric yield estimation considering leakage variability

Rajeev R. Rao;Anirudh Devgan;David Blaauw;Dennis Sylvester.
design automation conference (2004)

180 Citations

RC delay metrics for performance optimization

C.J. Alpert;A. Devgan;C.V. Kashyap.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2001)

177 Citations

Buffer insertion with accurate gate and interconnect delay computation

Charles J. Alpert;Anirudh Devgan;Stephen T. Quay.
design automation conference (1999)

152 Citations

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