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Tsutomu Sasao

Tsutomu Sasao

D-Index & Metrics

Computer Science

D-Index
39
Citations
7317
World Ranking
9679
National Ranking
140

Research.com Recognitions

  • 1994 - IEEE Fellow For contributions to the design theory and techniques of combinational logic circuits.

Overview

Tsutomu Sasao is affiliated with Meiji University in Japan. Their research contributions have been recognized with the IEEE Fellow award in 1994, honoring their work on the design theory and techniques of combinational logic circuits.

Sasao's primary areas of research focus on combinational logic circuits, particularly the design theories and techniques that underpin these essential components of digital systems.

Throughout their career, Sasao has worked without a recorded list of frequent co-authors or collaborative partnerships documented here. Similarly, there is no specified record of recent papers, publication venues, or book publications available at this time.

This profile reflects Sasao's documented affiliation, award recognition, and general field of study without additional publication or collaboration data.

Best Publications

  • Switching Theory for Logic Synthesis

    Tsutomu Sasao

  • Representations of Discrete Functions

    Tsutomu Sasao;Masahira Fujita

  • Logic Synthesis and Optimization

    Tsutomu Sasao

  • On the complexity of mod-2l sum PLA's

    T. Sasao;P. Besslich

  • Logic Synthesis and Verification

    Soha Hassoun;Tsutomu Sasao

  • EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions

    T. Sasao

  • FPGA Design by Generalized Functional Decomposition

    Tsutomu Sasao

  • Easily testable realizations for generalized Reed-Muller expressions

    T. Sasao

  • Memory-Based Logic Synthesis

    Tsutomu Sasao

  • On the optimal design of multiple-valued PLAs

    T. Sasao

  • Representations of Logic Functions Using EXOR Operators

    Tsutomu Sasao

  • A method to represent multiple-output switching functions by using multi-valued decision diagrams

    T. Sasao;J.T. Butler

  • A cascade realization of multiple-output function for reconfigurable hardware

    T. Sasao

  • Numerical Function Generators Using LUT Cascades

    T. Sasao;S. Nagayama;J.T. Butler

  • Selection of potentially testable path delay faults for test generation

    A. Murakami;S. Kajihara;T. Sasao;I. Pomeranz

  • Ternary decision diagrams. Survey

    T. Sasao

  • A deep convolutional neural network based on nested residue number system

    Hiroki Nakahara;Tsutomu Sasao

  • Minimization of AND-EXOR expressions using rewrite rules

    D. Brand;T. Sasao

  • Average path length of binary decision diagrams

    J.T. Butler;T. Sasao;M. Matsuura

  • Spectral Transform Decision Diagrams

    Radomir S. Stanković;Tsutomu Sasao;Claudio Moraga

  • EXMIN: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued input two-valued output functions

    T. Sasao

Frequent Co-Authors

Alan Mishchenko
Alan Mishchenko University of California, Berkeley
Xiaoqing Wen
Xiaoqing Wen Kyushu Institute of Technology
Marek Perkowski
Marek Perkowski Portland State University
Jaakko Astola
Jaakko Astola Tampere University
Irith Pomeranz
Irith Pomeranz Purdue University West Lafayette
Sudhakar M. Reddy
Sudhakar M. Reddy University of Iowa
Tohru Nagao
Tohru Nagao Ehime University
Robert K. Brayton
Robert K. Brayton University of California, Berkeley
Seiji Kajihara
Seiji Kajihara Kyushu Institute of Technology

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