1994 - IEEE Fellow For contributions to the design theory and techniques of combinational logic circuits.
Tsutomu Sasao mostly deals with Logic synthesis, Algorithm, Theoretical computer science, ExOR and Field-programmable gate array. His Logic synthesis research incorporates elements of Programmable logic array, Programming language and Arithmetic. His study in Algorithm is interdisciplinary in nature, drawing from both Function, Set, Benchmark and Minification.
In his study, Symmetric function is strongly linked to Exclusive or, which falls under the umbrella field of Minification. When carried out as part of a general Theoretical computer science research project, his work on Binary decision diagram is frequently linked to work in Functional verification, therefore connecting diverse disciplines of study. His Field-programmable gate array study integrates concerns from other disciplines, such as Lookup table, Cad tools and Reduction.
His main research concerns Algorithm, Function, Discrete mathematics, Binary decision diagram and Logic synthesis. Tsutomu Sasao combines subjects such as Theoretical computer science, Benchmark and Minification with his study of Algorithm. He interconnects Lookup table, Set, Realization and Arithmetic in the investigation of issues within Function.
Tsutomu Sasao has researched Discrete mathematics in several fields, including Upper and lower bounds, Variable, Combinatorics and Integer. His work in Binary decision diagram addresses issues such as Binary number, which are connected to fields such as Electronic circuit. His work on Logic optimization and Logic family is typically connected to ExOR as part of general Logic synthesis study, connecting several disciplines of science.
His scientific interests lie mostly in Index, Function, Algorithm, Field-programmable gate array and Computer hardware. His Function research integrates issues from Decision tree, Set, Combinatorics and Benchmark. In the field of Algorithm, his study on Logic synthesis overlaps with subjects such as Redundancy.
His research in Logic synthesis intersects with topics in Digital electronics and Heuristic. Lookup table is closely connected to Parallel computing in his research, which is encompassed under the umbrella topic of Field-programmable gate array. His Linear map study combines topics from a wide range of disciplines, such as Discrete mathematics and Functional decomposition.
Tsutomu Sasao mainly focuses on Index, Linear map, Field-programmable gate array, Function and Algorithm. The various areas that Tsutomu Sasao examines in his Linear map study include Discrete mathematics and Functional decomposition. His Field-programmable gate array research includes elements of Artificial neural network, Computer architecture and Parallel computing.
His biological study spans a wide range of topics, including Decision tree and Logic synthesis. His studies deal with areas such as Time complexity, Binary decision diagram, Heuristic and Benchmark as well as Logic synthesis. His Algorithm study combines topics from a wide range of disciplines, such as Decomposition and Pattern matching.
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Switching Theory for Logic Synthesis
Representations of Discrete Functions
Tsutomu Sasao;Masahira Fujita.
Logic Synthesis and Optimization
On the complexity of mod-2l sum PLA's
T. Sasao;P. Besslich.
IEEE Transactions on Computers (1990)
Logic Synthesis and Verification
Soha Hassoun;Tsutomu Sasao.
EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1993)
FPGA Design by Generalized Functional Decomposition
Easily testable realizations for generalized Reed-Muller expressions
IEEE Transactions on Computers (1997)
And-Exor Expressions and their Optimization
On the optimal design of multiple-valued PLAs
IEEE Transactions on Computers (1989)
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