2006 - ACM Paris Kanellakis Theory and Practice Award For leading the development and practical realization of algorithms for logic synthesis and for electronic system simulation, thereby helping to create key enabling technologies for the Electronic Design Automation industry.
1993 - Member of the National Academy of Engineering For contributions to the theory and practice of computer-aided analysis and design of electrical and logical circuits and systems.
1981 - IEEE Fellow For pioneering work in the theory of nonlinear networks, stability theory, and sparse matrix techniques.
Robert K. Brayton mainly investigates Algorithm, Theoretical computer science, Logic synthesis, Combinational logic and Logic optimization. His Algorithm research includes themes of Field-programmable gate array and Node. His research in Theoretical computer science intersects with topics in Finite-state machine and Algorithm design.
His Logic synthesis research incorporates elements of Computability and Implicant. His Combinational logic study integrates concerns from other disciplines, such as Boolean circuit, Speedup, Parallel computing and Boolean algebra. His Logic optimization research integrates issues from Signature, Sequential logic, Gate array and Arithmetic.
Robert K. Brayton spends much of his time researching Algorithm, Theoretical computer science, Logic synthesis, Sequential logic and Boolean function. His studies in Algorithm integrate themes in fields like Mathematical optimization and Set. His Theoretical computer science study frequently involves adjacent topics like Computation.
His Logic synthesis research focuses on Logic optimization in particular. His work carried out in the field of Logic optimization brings together such families of science as Register-transfer level, Pass transistor logic, Asynchronous circuit and Logic family. Robert K. Brayton has included themes like Digital electronics and Retiming, Parallel computing in his Sequential logic study.
The scientist’s investigation covers issues in Algorithm, Theoretical computer science, Logic synthesis, Boolean function and Sequential logic. His biological study spans a wide range of topics, including Set and Parallel computing. Robert K. Brayton has researched Theoretical computer science in several fields, including Finite-state machine, State and And-inverter graph.
His Logic synthesis research entails a greater understanding of Logic gate. In his work, Computer engineering is strongly intertwined with Netlist, which is a subfield of Boolean function. His Sequential logic research incorporates themes from Transformation, Combinational logic and Speedup.
Algorithm, Theoretical computer science, Sequential logic, Formal equivalence checking and Logic synthesis are his primary areas of study. The concepts of his Algorithm study are interwoven with issues in Interpolation, Electronic design automation and Parallel computing. His Theoretical computer science research is multidisciplinary, relying on both Boolean function, And-inverter graph and Netlist.
His Sequential logic study combines topics from a wide range of disciplines, such as Redundancy, Combinational logic and Speedup. His work in Logic synthesis tackles topics such as Standard cell which are related to areas like Graph, Computer hardware, Real-time computing, Digital electronics and Design flow. His Binary decision diagram research focuses on subjects like State, which are linked to Finite-state machine.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Logic Minimization Algorithms for VLSI Synthesis
Robert King Brayton;Alberto L. Sangiovanni-Vincentelli;Curtis T. McMullen;Gary D. Hachtel.
(1984)
Logic Minimization Algorithms for VLSI Synthesis
Robert King Brayton;Alberto L. Sangiovanni-Vincentelli;Curtis T. McMullen;Gary D. Hachtel.
(1984)
MIS: A Multiple-Level Logic Optimization System
R.K. Brayton;R. Rudell;A. Sangiovanni-Vincentelli;A.R. Wang.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1987)
MIS: A Multiple-Level Logic Optimization System
R.K. Brayton;R. Rudell;A. Sangiovanni-Vincentelli;A.R. Wang.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1987)
VIS: A System for Verification and Synthesis
Robert K. Brayton;Gary D. Hachtel;Alberto L. Sangiovanni-Vincentelli;Fabio Somenzi.
computer aided verification (1996)
VIS: A System for Verification and Synthesis
Robert K. Brayton;Gary D. Hachtel;Alberto L. Sangiovanni-Vincentelli;Fabio Somenzi.
computer aided verification (1996)
ABC: an academic industrial-strength verification tool
Robert Brayton;Alan Mishchenko.
computer aided verification (2010)
ABC: an academic industrial-strength verification tool
Robert Brayton;Alan Mishchenko.
computer aided verification (2010)
Logic verification using binary decision diagrams in a logic synthesis environment
S. Malik;A.R. Wang;R.K. Brayton;A. Sangiovanni-Vincentelli.
international conference on computer aided design (1988)
Logic verification using binary decision diagrams in a logic synthesis environment
S. Malik;A.R. Wang;R.K. Brayton;A. Sangiovanni-Vincentelli.
international conference on computer aided design (1988)
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