2023 - Research.com Computer Science in Canada Leader Award
2023 - Research.com Electronics and Electrical Engineering in Canada Leader Award
2012 - Fellow of the Royal Society of Canada Academy of Science
2011 - Member of the National Academy of Engineering For contributions to research and engineering of field-programmable gate array architectures and computer-aided design tools.
2009 - IEEE Fellow For contributions to field-programmable gate arrays
2008 - ACM Fellow For contributions to the architecture and computer-aided design of field-programmable gate arrays (FPGAs).
His primary areas of investigation include Field-programmable gate array, Embedded system, Computer architecture, Routing and Parallel computing. Jonathan Rose studies Field-programmable gate array, namely Logic block. His Embedded system research focuses on subjects like Software, which are linked to Adder, Static timing analysis, Energy consumption, Compile time and Netlist.
His Routing research is multidisciplinary, incorporating perspectives in Multiplexer, Stratix and Reduction. His biological study spans a wide range of topics, including Cluster based, Virtex, Cad flow and Router. His Logic synthesis study combines topics from a wide range of disciplines, such as Programmable logic array, Programmable logic device and Gate array.
Jonathan Rose mostly deals with Field-programmable gate array, Embedded system, Computer architecture, Routing and Parallel computing. His Field-programmable gate array study incorporates themes from Lookup table, Logic synthesis and Electronic circuit. His research integrates issues of Software and Interconnection in his study of Embedded system.
His Computer architecture research integrates issues from Applications architecture, Programmable logic device, Logic gate and Application-specific integrated circuit. His work in Routing covers topics such as Integrated circuit which are related to areas like Very-large-scale integration. His Speedup study in the realm of Parallel computing connects with subjects such as Function.
Field-programmable gate array, Embedded system, Computer architecture, Software and Computer hardware are his primary areas of study. Specifically, his work in Field-programmable gate array is concerned with the study of Logic block. The concepts of his Embedded system study are interwoven with issues in Interconnection, Out-of-order execution and Graphics.
Jonathan Rose focuses mostly in the field of Computer architecture, narrowing it down to topics relating to Verilog and, in certain cases, Software suite, Benchmark and Software architecture description. His work on Nios II and Reconfigurable computing as part of general Software research is often related to Throughput, thus linking different fields of science. His Computer hardware research also works with subjects such as
Jonathan Rose mainly focuses on Field-programmable gate array, Embedded system, Software, Computer architecture and Adder. His Field-programmable gate array study combines topics in areas such as Logic synthesis, Circuit design and Parallel computing. His Embedded system course of study focuses on Multi-core processor and Solver, Stratix, FPGA prototype, Hardware description language and Reconfigurable computing.
His work carried out in the field of Software brings together such families of science as Program optimization, Component and Graphics. His Computer architecture research includes themes of Lookup table, Routing, Logic block and Verilog. The various areas that he examines in his Routing study include Logic gate and Benchmark.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Measuring the Gap Between FPGAs and ASICs
I. Kuon;J. Rose.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2007)
Architecture and CAD for Deep-Submicron FPGAS
Vaughn Betz;Jonathan Rose;Alexander Marquardt.
(1999)
VPR: A new packing, placement and routing tool for FPGA research
Vaughn Betz;Jonathan Rose.
field programmable logic and applications (1997)
The effect of LUT and cluster size on deep-submicron FPGA performance and density
E. Ahmed;J. Rose.
international symposium on low power electronics and design (2004)
FPGA Architecture: Survey and Challenges
Ian Kuon;Russell Tessier;Jonathan Rose.
(2008)
Architecture of field-programmable gate arrays
J. Rose;A. El Gamal;A. Sangiovanni-Vincentelli.
Proceedings of the IEEE (1993)
FPGA and CPLD architectures: a tutorial
S. Brown;J. Rose.
IEEE Design & Test of Computers (1996)
Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency
J. Rose;R.J. Francis;D. Lewis;P. Chow.
IEEE Journal of Solid-state Circuits (1990)
VTR 7.0: Next Generation Architecture and CAD System for FPGAs
Jason Luu;Jeffrey Goeders;Michael Wainberg;Andrew Somerville.
ACM Transactions on Reconfigurable Technology and Systems (2014)
Chortle-crf: Fast technology mapping for lookup table-based FPGAs
Robert Francis;Jonathan Rose;Zvonko Vranesic.
design automation conference (1991)
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