World's Best Scientists 2026 revealed!

D-Index & Metrics

Computer Science

D-Index
37
Citations
6855
World Ranking
10620
National Ranking
422

Research.com Recognitions

  • 2019 - IEEE Fellow For contributions to the programmability of FPGA-based computing

Overview

Paul Chow is affiliated with the University of Toronto in Canada and has contributed primarily to the field of Computer Science, with a concentration on several subfields including Computer Networks and Communications, Hardware and Architecture, Electrical and Electronic Engineering, Information Systems, and Artificial Intelligence.

Their research spans various topics, notably:

  • Advanced Data Storage Technologies
  • Cloud Computing and Resource Management
  • Parallel Computing and Optimization Techniques
  • Distributed and Parallel Computing Systems
  • Interconnection Networks and Systems
  • Physical Unclonable Functions (PUFs) and Hardware Security
  • Radiation Effects in Electronics

Frequent publication venues for their work include:

  • arXiv (Cornell University)
  • ACM Transactions on Reconfigurable Technology and Systems
  • IEEE Access
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Journal of Optical Communications and Networking

Among recent papers authored or co-authored by Paul Chow are:

  • The Future of FPGA Acceleration in Datacenters and the Cloud (2022), published in ACM Transactions on Reconfigurable Technology and Systems
  • Disaggregated Memory in the Datacenter: A Survey (2023), published in IEEE Access
  • FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction (2020), published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • AIgean: An Open Framework for Deploying Machine Learning on Heterogeneous Clusters (2021), published in ACM Transactions on Reconfigurable Technology and Systems
  • RIFL: a reliable link layer network protocol for data center communication (2021), published in Journal of Optical Communications and Networking

Paul Chow's research collaborations include frequent co-authors such as Mohammad Ewais, Qianfeng Shen, Naif Tarafdar, Juan Camilo Vega, and Christophe Bobda, reflecting interdisciplinary teamwork across different studies and projects.

Recognition of their contributions includes the IEEE Fellow award granted in 2019 for contributions to the programmability of FPGA-based computing.

Best Publications

  • Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency

    J. Rose;R.J. Francis;D. Lewis;P. Chow

  • OneChip: An FPGA Processor With Reconfigurable Logic

    Ralph Wittig;Paul Chow

  • The multicluster architecture: reducing cycle time through partitioning

    Keith I. Farkas;Paul Chow;Norman P. Jouppi;Zvonko Vranesic

  • FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack

    Stuart Byma;J. Gregory Steffan;Hadi Bannazadeh;Alberto Leon Garcia

  • The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout

    P. Chow;Soon Ong Seo;J. Rose;K. Chung

  • The design of an SRAM-based field-programmable gate array. I. Architecture

    P. Chow;Soon Ong Seo;J. Rose;K. Chung

  • Memory interfacing and instruction specification for reconfigurable processors

    Jeffrey A. Jacob;Paul Chow

  • Register file design considerations in dynamically scheduled processors

    K.I. Farkas;N.P. Jouppi;P. Chow

  • The effect of logic block architecture on FPGA performance

    S. Singh;J. Rose;P. Chow;D. Lewis

  • Exploiting dual data-memory banks in digital signal processors

    Mazen A. R. Saghir;Paul Chow;Corinna G. Lee

  • The effect of reconfigurable units in superscalar processors

    Jorge E. Carrillo;Paul Chow

  • TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs

    Manuel Saldana;Paul Chow

  • MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache

    M. Horowitz;P. Chow;D. Stark;R.T. Simoni

  • Reconfigurable molecular dynamics simulator

    N. Azizi;I. Kuon;A. Egier;A. Darabiha

  • Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks

    Roberto DiCecco;Griffin Lacey;Jasmina Vasiljevic;Paul Chow

  • Memory-system design considerations for dynamically-scheduled processors

    Keith I. Farkas;Paul Chow;Norman P. Jouppi;Zvonko Vranesic

  • The Transmogrifier-2: a 1 million gate rapid-prototyping system

    D.M. Lewis;D.R. Galloway;M. Van Ierssel;J. Rose

  • Architectural tradeoffs in the design of MIPS-X

    P. Chow;M. Horowitz

  • How useful are non-blocking loads, stream buffers and speculative execution in multiple issue processors?

    K.I. Farkas;N.P. Jouppi;P. Chow

  • Using reconfigurability to achieve real-time profiling for hardware/software codesign

    Lesley Shannon;Paul Chow

Frequent Co-Authors

Alberto Leon-Garcia
Alberto Leon-Garcia University of Toronto
Jonathan Rose
Jonathan Rose University of Toronto
Mark Horowitz
Mark Horowitz Stanford University
David Lewis
David Lewis University of Adelaide
John L. Hennessy
John L. Hennessy Stanford University
Norman P. Jouppi
Norman P. Jouppi Google (United States)
Vaughn Betz
Vaughn Betz University of Toronto
Shaojun Wei
Shaojun Wei Tsinghua University

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