2026 Jason H. Anderson: Electronics and Electrical Engineering Researcher – H-Index, Publications & Awards

Discipline name	D-Index	World Ranking	Current World Ranking	National Ranking	Current National Ranking	Publications	Citations
Electronics and Electrical Engineering	32	6210	5964	272	254	143	6164

Research.com Recognitions

2013 - ACM Fellow For contributions to the implementation and analysis of multiprocessor and multicore real-time systems.

Overview

Jason H. Anderson is affiliated with the University of Toronto in Canada. Their research activity centers on hardware and architecture within the broader fields of computer science and engineering.

The scientist's main fields of study include:

Computer Science
Engineering

Their investigations extend into several subfields such as:

Hardware and Architecture
Electrical and Electronic Engineering
Computational Theory and Mathematics
Artificial Intelligence
Computer Networks and Communications

Key topics explored in their research are:

VLSI and FPGA Design Techniques
Embedded Systems Design Techniques
VLSI and Analog Circuit Testing
Evolutionary Algorithms and Applications
Low-power high-performance VLSI design
Numerical Methods and Algorithms
Parallel Computing and Optimization Techniques

Jason H. Anderson has published in a variety of venues, including:

2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
Proceedings of the 28th Asia and South Pacific Design Automation Conference
2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computers

Some of their recent papers are:

"Optimizing FPGA Logic Block Architectures for Arithmetic," 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems
"Area-Driven FPGA Logic Synthesis Using Reinforcement Learning," 2023, Proceedings of the 28th Asia and South Pacific Design Automation Conference
"Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code," 2021, IEEE Transactions on Computers
"Elastic Multi-Context CGRAs," 2022, 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
"CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams," 2022, 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)

Frequent co-authors collaborating with Jason H. Anderson include:

Rami Beidas
Guanglei Zhou
Kevin E. Murray
Jason Luu
Matthew Walker

Among awards received, Jason H. Anderson was named an ACM Fellow in 2013 for contributions to the implementation and analysis of multiprocessor and multicore real-time systems.

Best Publications

LegUp: high-level synthesis for FPGA-based processor/accelerator systems

Andrew Canis;Jongsok Choi;Mark Aldham;Victor Zhang

765
Citations
A Survey and Evaluation of FPGA High-Level Synthesis Tools

Razvan Nane;Vlad-Mihai Sima;Christian Pilato;Jongsok Choi

670
Citations
VTR 7.0: Next Generation Architecture and CAD System for FPGAs

Jason Luu;Jeffrey Goeders;Michael Wainberg;Andrew Somerville

451
Citations
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems

Andrew Canis;Jongsok Choi;Mark Aldham;Victor Zhang

432
Citations
The VTR project: architecture and CAD for FPGAs from verilog to routing

Jonathan Rose;Jason Luu;Chi Wai Yu;Opal Densmore

357
Citations
Active leakage power optimization for FPGAs

J.H. Anderson;F.N. Najm

239
Citations
Active leakage power optimization for FPGAs

Jason H. Anderson;Farid N. Najm;Tim Tuan

234
Citations
A PUF design for secure FPGA-based embedded systems

Jason H. Anderson

167
Citations
Power estimation techniques for FPGAs

J.H. Anderson;F.N. Najm

160
Citations
CGRA-ME: A unified framework for CGRA modelling and exploration

S. Alexander Chin;Noriaki Sakamoto;Allan Rui;Jim Zhao

158
Citations
A PUF design for secure FPGA-based embedded systems

Unknown

118
Citations
From software threads to parallel hardware in high-level synthesis for FPGAs

Jongsok Choi;Stephen Brown;Jason Anderson

107
Citations
Analytical placement for heterogeneous FPGAs

Marcel Gort;Jason H. Anderson

104
Citations
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect

Jason Luu;Jason Helge Anderson;Jonathan Scott Rose

102
Citations
Power-aware technology mapping for LUT-based FPGAs

J.H. Anderson;F.N. Najm

97
Citations
Method for application of network flow techniques under constraints

Jason H. Anderson;Sudip K. Nag;Guenter Stenz;Srinivasan Dasasathyan

96
Citations
Clock gating architectures for FPGA power reduction

Safeen Huda;Muntasir Mallick;Jason H. Anderson

92
Citations
Source-level debugging for FPGA high-level synthesis

Nazanin Calagar;Stephen D. Brown;Jason H. Anderson

87
Citations
Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems

Jongsok Choi;Kevin Nam;Andrew Canis;Jason Anderson

83
Citations
Low-power programmable routing circuitry for FPGAs

James H. Anderson;F. N. Najm

78
Citations
Impact of FPGA architecture on resource sharing in high-level synthesis

Stefan Hadjis;Andrew Canis;Jason H. Anderson;Jongsok Choi

74
Citations
Low-Power Programmable FPGA Routing Circuitry

J.H. Anderson;F.N. Najm

73
Citations
A novel low-power FPGA routing switch

J.H. Anderson;F.N. Najm

73
Citations
Technology mapping for large complex PLDs

Jason Helge Anderson;Stephen Dean Brown

73
Citations

Frequent Co-Authors

Farid N. Najm University of Toronto

Jonathan Rose University of Toronto

Vaughn Betz University of Toronto

Philip H. W. Leong University of Sydney

Wayne Luk Imperial College London

Luca P. Carloni Columbia University

External Links

Personal website of Jason H. Anderson

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