John Wawrzynek mainly investigates Parallel computing, Field-programmable gate array, Computer architecture, Reconfigurable computing and Compiler. The various areas that John Wawrzynek examines in his Parallel computing study include Virtual Processor, Process, Very-large-scale integration and Dram. His Field-programmable gate array study integrates concerns from other disciplines, such as Time complexity, Functional programming and Leverage.
His Computer architecture study combines topics in areas such as Coprocessor, Fraction, Range, Software and Computation. His Reconfigurable computing study combines topics from a wide range of disciplines, such as Logic synthesis, Software deployment, Interconnection and Component. His Compiler research includes elements of Dynamic programming, Abstract machine and Finite state machine with datapath, Datapath.
John Wawrzynek spends much of his time researching Field-programmable gate array, Embedded system, Parallel computing, Computer architecture and Computer hardware. His work in the fields of Field-programmable gate array, such as Reconfigurable computing, intersects with other areas such as Emulation and Throughput. His research in Embedded system intersects with topics in Instruction set and Signal processing.
He combines subjects such as Compiler and Static random-access memory with his study of Parallel computing. His Computer architecture research is multidisciplinary, incorporating perspectives in Multithreading and Computation. His Computer hardware research also works with subjects such as
The scientist’s investigation covers issues in Field-programmable gate array, Embedded system, Parallel computing, Speedup and Context. John Wawrzynek interconnects Computer architecture, Key and Software in the investigation of issues within Field-programmable gate array. His Computer architecture research includes themes of Overlay and Latency.
His specific area of interest is Embedded system, where he studies Reconfigurable computing. His Reconfigurable computing research is multidisciplinary, relying on both Block, MicroBlaze and Benchmark. His work in the fields of Parallel computing, such as Memory architecture, overlaps with other areas such as Resistive random-access memory.
John Wawrzynek spends much of his time researching Field-programmable gate array, Cloud computing, Computer hardware, Co-design and Task. The Field-programmable gate array study combines topics in areas such as Data access, Software, Memory bandwidth and Computer architecture. The study incorporates disciplines such as Computer security, Enhanced Data Rates for GSM Evolution and Forwarding plane in addition to Cloud computing.
His studies in Computer hardware integrate themes in fields like Exploit, Artificial neural network, Embedded hardware and Key. As part of the same scientific family, John Wawrzynek usually focuses on Distributed computing, concentrating on Component and intersecting with Embedded system. His Hardware acceleration study, which is part of a larger body of work in Embedded system, is frequently linked to Throughput, bridging the gap between disciplines.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Garp: a MIPS processor with a reconfigurable coprocessor
J.R. Hauser;J. Wawrzynek.
field programmable custom computing machines (1997)
A view of the parallel computing landscape
Krste Asanovic;Rastislav Bodik;James Demmel;Tony Keaveny.
parallel computing (2009)
The Garp architecture and C compiler
T.J. Callahan;J.R. Hauser;J. Wawrzynek.
IEEE Computer (2000)
Chisel: constructing hardware in a Scala embedded language
Jonathan Bachrach;Huy Vo;Brian Richards;Yunsup Lee.
design automation conference (2012)
Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine
David E. Culler;Anurag Sah;Klaus E. Schauser;Thorsten von Eicken.
architectural support for programming languages and operating systems (1991)
Reconfigurable computing: what, why, and implications for design automation
André DeHon;John Wawrzynek.
design automation conference (1999)
BEE2: a high-end reconfigurable computing system
C. Chang;J. Wawrzynek;R.W. Brodersen.
IEEE Design & Test of Computers (2005)
Stream Computations Organized for Reconfigurable Execution (SCORE)
Eylon Caspi;Michael Chu;Randy Huang;Joseph Yeh.
field programmable logic and applications (2000)
HSRA: high-speed, hierarchical synchronous reconfigurable array
William Tsu;Kip Macy;Atul Joshi;Randy Huang.
field programmable gate arrays (1999)
Silicon auditory processors as computer peripherals
J. Lazzaro;J. Wawrzynek;M. Mahowald;M. Sivilotti.
IEEE Transactions on Neural Networks (1993)
If you think any of the details on this page are incorrect, let us know.
We appreciate your kind effort to assist us to improve this page, it would be helpful providing us with as much detail as possible in the text box below: