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Computer Science

D-Index
52
Citations
8540
World Ranking
5164
National Ranking
2373

Electronics and Electrical Engineering

D-Index
51
Citations
8356
World Ranking
2718
National Ranking
1030

Overview

Ryan Kastner is affiliated with the University of California, San Diego in the United States. Their research spans the fields of Computer Science and Engineering, with a particular focus on subfields such as Artificial Intelligence, Hardware and Architecture, Electrical and Electronic Engineering, Signal Processing, and Computer Vision and Pattern Recognition.

Their main topics of work include:

  • Physical Unclonable Functions (PUFs) and Hardware Security
  • Security and Verification in Computing
  • Advanced Malware Detection Techniques
  • Radiation Effects in Electronics
  • Advanced Neural Network Applications
  • Neural Networks and Applications
  • Parallel Computing and Optimization Techniques

Ryan Kastner has published extensively, with major contributions appearing in venues such as arXiv (Cornell University), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, the 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), IEEE Security & Privacy, and IEEE Transactions on Computers.

Some of their recent papers include:

  • "An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools" (2020) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • "Hardware Information Flow Tracking" (2021) published in ACM Computing Surveys
  • "Target detection using features for sonar images" (2020) in IET Radar Sonar & Navigation
  • "Aker: A Design and Verification Framework for Safe and Secure SoC Access Control" (2021) presented at the 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
  • "Low-cost 3D scanning systems for cultural heritage documentation" (2020) in Journal of Cultural Heritage Management and Sustainable Development

The scientist frequently collaborates with a group of coauthors, including Andres Meza, Francesco Restuccia, Olivia Weng, J. Duarte, and Nhan Viet Tran.

Best Publications

  • Fast template placement for reconfigurable computing systems

    K. Bazargan;R. Kastner;M. Sarrafzadeh

  • Instruction generation for hybrid reconfigurable systems

    R. Kastner;A. Kaplan;S. Ogrenci Memik;E. Bozorgzadeh

  • RIFFA 2.1: A Reusable Integration Framework for FPGA Accelerators

    Matthew Jacobsen;Dustin Richmond;Matthew Hogains;Ryan Kastner

  • Fpga-based face detection system using Haar classifiers

    Junguk Cho;Shahnam Mirzaei;Jason Oberg;Ryan Kastner

  • A swarm of autonomous miniature underwater robot drifters for exploring submesoscale ocean dynamics

    Jules S. Jaffe;Peter J. S. Franks;Paul L. D. Roberts;Diba Mirza

  • Congestion estimation during top-down placement

    Xiaojian Yang;R. Kastner;M. Sarrafzadeh

  • An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

    Wei Hu;Chip-Hong Chang;Anirban Sengupta;Swarup Bhunia

  • Predictable routing

    Ryan Kastner;Elaheh Bozorgzadeh;Majid Sarrafzadeh

  • Pattern routing: use and theory for increasing predictability and avoiding coupling

    R. Kastner;E. Bozorgzadeh;M. Sarrafzadeh

  • FPGA Implementation of High Speed FIR Filters Using Add and Shift Method

    S. Mirzaei;A. Hosangadi;R. Kastner

  • Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs

    Daniel Hefenbrock;Jason Oberg;Nhat Tan Nguyen Thanh;Ryan Kastner

  • Instruction generation and regularity extraction for reconfigurable processors

    Philip Brisk;Adam Kaplan;Ryan Kastner;Majid Sarrafzadeh

  • Sapper: a language for hardware-level security policy enforcement

    Xun Li;Vineeth Kashyap;Jason K. Oberg;Mohit Tiwari

  • SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip

    Hassan M. G. Wassel;Ying Gao;Jason K. Oberg;Ted Huffmire

  • Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems

    T. Huffmire;B. Brotherton;Gang Wang;T. Sherwood

  • Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security

    Mohit Tiwari;Jason K. Oberg;Xun Li;Jonathan Valamehr

  • Register transfer level information flow tracking for provably secure hardware design

    Armaiti Ardeshiricham;Wei Hu;Joshua Marxen;Ryan Kastner

  • Design of a low-cost, underwater acoustic modem for short-range sensor networks

    B. Benson;Y. Li;R. Kastner;B. Faunce

  • Detecting Hardware Trojans with Gate-Level Information-Flow Tracking

    Wei Hu;Baolei Mao;Jason Oberg;Ryan Kastner

  • $O(N)$ O ( N ) -Space Spatiotemporal Filter for Reducing Noise in Neuromorphic Vision Sensors

    Alireza Khodamoradi;Ryan Kastner

  • Instruction generation for hybrid reconfigurable systems

    Ryan Kastner;Seda Ogrenci-Memik;Elaheh Bozorgzadeh;Majid Sarrafzadeh

  • RIFFA 2.0: A reusable integration framework for FPGA accelerators

    Matthew Jacobsen;Ryan Kastner

Frequent Co-Authors

Timothy Sherwood
Timothy Sherwood University of California, Santa Barbara
Majid Sarrafzadeh
Majid Sarrafzadeh University of California, Los Angeles
Wei Hu
Wei Hu Nanjing University
Curt Schurgers
Curt Schurgers University of California, San Diego
Frederic T. Chong
Frederic T. Chong University of Chicago
Philip Brisk
Philip Brisk University of California, Riverside
Serge Belongie
Serge Belongie University of Copenhagen
Rajesh Gupta
Rajesh Gupta University of California, San Diego
Paolo Ienne
Paolo Ienne École Polytechnique Fédérale de Lausanne
Dino Di Carlo
Dino Di Carlo University of California, Los Angeles

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