2008 - Fellow of the American Association for the Advancement of Science (AAAS)
2005 - IEEE Fellow For contributions to design automation of digital systems and to reconfigurable computing.
Fadi J. Kurdahi mostly deals with Computer architecture, Embedded system, Parallel computing, Reduced instruction set computing and Reconfigurable computing. Fadi J. Kurdahi combines subjects such as System on a chip, Dynamic priority scheduling, SIMD and Instruction register with his study of Computer architecture. His Embedded system study combines topics in areas such as Data compression, Control power, Bandwidth and Pattern recognition.
His Parallel computing research is multidisciplinary, incorporating elements of Field-programmable gate array, High-level synthesis, Compiler, Decoding methods and Sequential decoding. Fadi J. Kurdahi has included themes like Evolvable hardware, Granularity and Chip in his Reduced instruction set computing study. The concepts of his Reconfigurable computing study are interwoven with issues in Scheduling, Processor scheduling, Two-level scheduling, Application domain and Encryption.
His primary areas of study are Embedded system, Electronic engineering, Computer architecture, Parallel computing and High-level synthesis. His Embedded system study integrates concerns from other disciplines, such as Energy consumption, Control reconfiguration and Wireless. His studies deal with areas such as Redundancy and Communication channel as well as Wireless.
His Electronic engineering research is multidisciplinary, incorporating perspectives in Chip and Voltage. Fadi J. Kurdahi interconnects SIMD, Reconfigurable computing, Scheduling and Reduced instruction set computing in the investigation of issues within Computer architecture. He has researched High-level synthesis in several fields, including Computer engineering and Engineering design process.
Fadi J. Kurdahi focuses on Memristor, Crossbar switch, Artificial intelligence, Electronic engineering and Artificial neural network. The Memristor study combines topics in areas such as Scalability, Resistive random-access memory, Energy consumption, Inference and Parallel computing. His Parallel computing research incorporates elements of Scheme, Reconfigurable computing and Finite impulse response.
His work in the fields of Spice overlaps with other areas such as Matrix multiplication. His Gradient descent research integrates issues from Computational neuroscience, Computer architecture, Hardware architecture and Computer engineering. His research investigates the connection between Embedded system and topics such as Focus that intersect with issues in Reliability.
Fadi J. Kurdahi spends much of his time researching Crossbar switch, Memristor, Artificial neural network, Artificial intelligence and Spiking neural network. His Crossbar switch study is concerned with the larger field of Electronic engineering. His research in Electronic engineering intersects with topics in Voltage drop, Elmore delay and Parallel processing.
His Memristor study incorporates themes from Computer architecture, Capacitive sensing, Parasitic extraction, Transient and Inductance. Fadi J. Kurdahi incorporates Computer architecture and Flexibility in his studies. Within one scientific family, Fadi J. Kurdahi focuses on topics pertaining to Gradient descent under Spiking neural network, and may sometimes address concerns connected to Computational neuroscience, Computer engineering and Very-large-scale integration.
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MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications
H. Singh;Ming-Hau Lee;Guangming Lu;F.J. Kurdahi.
IEEE Transactions on Computers (2000)
MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications
H. Singh;Ming-Hau Lee;Guangming Lu;F.J. Kurdahi.
IEEE Transactions on Computers (2000)
REAL: A Program for REgister ALlocation
F. J. Kurdahi;A. C. Parker.
design automation conference (1987)
REAL: A Program for REgister ALlocation
F. J. Kurdahi;A. C. Parker.
design automation conference (1987)
Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor
Ming-Hau Lee;Hartej Singh;Guangming Lu;Nader Bagherzadeh.
signal processing systems (2000)
Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor
Ming-Hau Lee;Hartej Singh;Guangming Lu;Nader Bagherzadeh.
signal processing systems (2000)
Power-aware scheduling under timing constraints for mission-critical embedded systems
Jinfeng Liu;Pai H. Chou;Nader Bagherzadeh;Fadi Kurdahi.
design automation conference (2001)
Power-aware scheduling under timing constraints for mission-critical embedded systems
Jinfeng Liu;Pai H. Chou;Nader Bagherzadeh;Fadi Kurdahi.
design automation conference (2001)
Techniques for area estimation of VLSI layouts
F.J. Kurdahi;A.C. Parker.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1989)
Techniques for area estimation of VLSI layouts
F.J. Kurdahi;A.C. Parker.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1989)
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