World's Best Scientists 2026 revealed!

Overview

Ranga Vemuri is affiliated with the University of Cincinnati in the United States and focuses research efforts primarily in the fields of Computer Science and Engineering. Their work covers subfields such as Hardware and Architecture, Electrical and Electronic Engineering, Artificial Intelligence, Computational Theory and Mathematics, and Signal Processing.

The topics Ranga Vemuri frequently investigates include:

  • Physical Unclonable Functions (PUFs) and Hardware Security
  • Integrated Circuits and Semiconductor Failure Analysis
  • Cryptographic Implementations and Security
  • Embedded Systems Design Techniques
  • VLSI and FPGA Design Techniques
  • Advanced Memory and Neural Computing
  • VLSI and Analog Circuit Testing

Recent publications highlight their involvement with logic encryption, hardware design verification, and security schemes. Selected papers include:

  • "Logic Encryption for Resource Constrained Designs," 2021, IEEE Access
  • "Analysis of the Satisfiability Attack Against Logic Encryption Using Synthetic Benchmarks," 2022, 2022 IEEE International Symposium on Smart Electronic Systems (iSES)
  • "Model Checking Leveraged Error Localization for Complex RTL Designs," 2022, 2022 IEEE 40th International Conference on Computer Design (ICCD)
  • "SRTLock: A Sensitivity Resilient Two-Tier Logic Encryption Scheme," 2021, 2021 IEEE International Symposium on Smart Electronic Systems (iSES)
  • "Efficient Method for Timing-based Information Flow Verification in Hardware Designs," 2022, Proceedings of the Great Lakes Symposium on VLSI 2022

Ranga Vemuri has collaborated frequently with several co-authors, including:

  • David Luria
  • Nikhil Saxena
  • Ram Venkat Narayanan
  • Kishore Pula
  • Sundarakumar Muthukumaran

The scientist's research contributions have been published in venues such as:

  • arXiv (Cornell University)
  • IEEE Access
  • 2022 IEEE International Symposium on Smart Electronic Systems (iSES)
  • 2022 IEEE 40th International Conference on Computer Design (ICCD)
  • 2021 IEEE International Symposium on Smart Electronic Systems (iSES)

Best Publications

  • An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications

    Meenakshi Kaul;Ranga Vemuri;Sriram Govindarajan;Iyad Ouaiss

  • Extraction and use of neural network models in automated synthesis of operational amplifiers

    G. Wolfe;R. Vemuri

  • An efficient algorithm for finding empty space for online FPGA placement

    Manish Handa;Ranga Vemuri

  • An integrated partitioning and synthesis system for dynamically reconfigurable Multi-FPGA architectures

    Iyad Ouaiss;Sriram Govindarajan;Vinoo Srinivasan;Meenakshi Kaul

  • An integrated multicomponent synthesis environment for MCMs

    R. Vemuri;N. Kumar;R. Vutukuru;P.S. Rao

  • Profile-driven behavioral synthesis for low-power VLSI systems

    N. Kumar;S. Katkoori;L. Rader;R. Vemuri

  • Hardware/software partitioning with integrated hardware design space exploration

    V. Srinivasan;S. Radhakrishnan;R. Vemuri

  • LiPaR: A light-weight parallel router for FPGA-based networks-on-chip

    Balasubramanian Sethuraman;Prasun Bhattacharya;Jawad Khan;Ranga Vemuri

  • DSS: a distributed high-level synthesis system

    J. Roy;N. Kumar;R. Dutta;R. Vemuri

  • Optimal temporal partitioning and synthesis for reconfigurable architectures

    M. Kaul;R. Vemuri

  • Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS

    A. Doboli;R. Vemuri

  • Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies

    A. Doboli;R. Vemuri

  • Distributed design-space exploration for high-level synthesis systems

    R. Dutta;J. Roy;R. Vemuri

  • Behavioral synthesis of analog systems using two-layered design space exploration

    Alex Doboli;Adrian Nunez-Aldana;Nagu Dhanwada;Sree Ganesan

  • Hardware-Software Codesign for Dynamically Reconfigurable Architectures

    Karam S. Chatha;Ranga Vemuri

  • An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms

    A. Das;R. Vemuri

  • Temporal partitioning combined with design space exploration for latency minimization of run-time reconfigured designs

    Meenakshi Kaul;Ranga Vemuri

  • Fast, layout-inclusive analog circuit synthesis using pre-compiled parasitic-aware symbolic performance models

    Mukesh Ranjan;Wim Verhaegen;Anuradha Agarwal;Hemanth Sampath

  • optiMap: a tool for automated generation of NoC architectures using multi-port routers for FPGAs

    B. Sethuraman;R. Vemuri

  • An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling

    Karam S. Chatha;Ranga Vemuri

Frequent Co-Authors

Yehia Massoud
Yehia Massoud Stevens Institute of Technology
Rajesh Gupta
Rajesh Gupta University of California, San Diego

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