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Diederik Verkest

Diederik Verkest

D-Index & Metrics

Computer Science

D-Index
51
Citations
9163
World Ranking
5393
National Ranking
61

Electronics and Electrical Engineering

D-Index
51
Citations
9203
World Ranking
2697
National Ranking
62

Overview

Diederik Verkest is affiliated with Imec in Belgium and works primarily in the fields of Engineering and Computer Science, with a focus on Electrical and Electronic Engineering, Artificial Intelligence, and Computer Vision and Pattern Recognition. Their research contributions span several interconnected domains including advanced memory and neural computing, ferroelectric and negative capacitance devices, and advanced neural network applications.

The scientist's publication record includes a series of recent papers that emphasize energy-efficient and hybrid neural network systems, analog in-memory computing, and semiconductor technologies. Notable papers include:

  • DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC, 2022, 2022 IEEE International Solid-State Circuits Conference (ISSCC)
  • DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge, 2022, IEEE Journal of Solid-State Circuits
  • IGZO-Based Compute Cell for Analog In-Memory Computing-DTCO Analysis to Enable Ultralow-Power AI at Edge, 2020, IEEE Transactions on Electron Devices
  • A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes, 2022, IEEE Transactions on Electron Devices
  • OxRRAM-Based Analog in-Memory Computing for Deep Neural Network Inference: A Conductance Variability Study, 2021, IEEE Transactions on Electron Devices

Their frequent coauthors include Peter Debacker (9 collaborations), Arindam Mallik (6), Debjyoti Bhattacharjee (5), Ioannis A. Papistas (4), and Jonas Doevenspeck (4).

Diederik Verkest has contributed multiple times to prominent publication venues. Among these:

  • IEEE Transactions on Electron Devices (3 publications)
  • 2022 IEEE International Symposium on Circuits and Systems (ISCAS) (2 publications)
  • 2022 IEEE International Solid-State Circuits Conference (ISSCC) (1 publication)
  • IEEE Journal of Solid-State Circuits (1 publication)
  • ACM Transactions on Design Automation of Electronic Systems (1 publication)

Their main research topics include:

  • Advanced Memory and Neural Computing
  • Ferroelectric and Negative Capacitance Devices
  • Advanced Neural Network Applications
  • Semiconductor materials and devices
  • Machine Learning and Extreme Learning Machines (ELM)
  • Neural Networks and Applications
  • CCD and CMOS Imaging Sensors

This collective body of work reflects a technical focus on energy-efficient computing architectures, neural network integration at the hardware level, and semiconductor device innovation directed towards enabling ultralow-power artificial intelligence systems, particularly for edge computing applications.

Best Publications

  • ADRES: an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable Matrix

    Bingfeng Mei;Serge Vernalde;Diederik Verkest;Hugo De Man

  • DRESC: a retargetable compiler for coarse-grained reconfigurable architectures

    Bingfeng Mei;S. Vernalde;D. Verkest;H. De Man

  • Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node

    Doyoung Jang;Dmitry Yakimets;Geert Eneman;Pieter Schuddinck

  • Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs

    Théodore Marescaux;Andrei Bartic;Diederik Verkest;Diederik Verkest;Serge Vernalde

  • Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling

    Bingfeng Mei;S. Vernalde;D. Verkest;H. De Man

  • Vertical GAAFETs for the Ultimate CMOS Scaling

    Dmitry Yakimets;Geert Eneman;Pieter Schuddinck;Trong Huynh Bao

  • 3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot

    P. Marchal;B. Bougard;G. Katti;M. Stucchi

  • Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip

    J.-Y. Mignolet;V. Nollet;P. Coene;D. Verkest

  • Architecture exploration for a reconfigurable architecture template

    Unknown

  • Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study

    Bingfeng Mei;Serge Vernalde;Diederik Verkest;Rudy Lauwereins

  • CoWare-a design environment for heterogeneous hardware/software systems

    K. Van Rompaey;D. Verkest;I. Bolsens;H. De Man

  • CoWare—A design environment for heterogeneous hardware/software systems

    Unknown

  • Hardware/software co-design of digital telecommunication systems

    I. Bolsens;H.J. De Man;B. Lin;K. Van Rompaey

  • Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles

    V. Nollet;T. Marescaux;P. Avasare;D. Verkest

  • Designing an operating system for a heterogeneous reconfigurable SoC

    V. Nollet;P. Coene;D. Verkest;S. Vernalde

  • Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs

    Unknown

  • Networks on chip as hardware components of an OS for reconfigurable systems

    Théodore Marescaux;Jean-Yves Mignolet;T. Andrei Bartic;W. Moffat

  • Impact of Wire Geometry on Interconnect RC and Circuit Delay

    Ivan Ciofi;Antonino Contino;Philippe J. Roussel;Rogier Baert

  • Operating-system controlled network on chip

    Vincent Nollet;Théodore Marescaux;Diederik Verkest;Jean-Yves Mignolet

  • Concurrent timed digital system design method and environment

    Johan Cockx;Diederik Verkest

  • Operating system based software generation for systems-on-chip

    D. Desmet;D. Verkest;H. De Man

  • Topology adaptive network-on-chip design and implementation

    T.A. Bartic;J.-Y. Mignolet;V. Nollet;T. Marescaux

  • Real-time high-definition stereo matching on FPGA

    Lu Zhang;Ke Zhang;Tian Sheuan Chang;Gauthier Lafruit

Frequent Co-Authors

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