Diederik Verkest mostly deals with Embedded system, Computer architecture, Field-programmable gate array, System on a chip and Reconfigurable computing. The concepts of his Embedded system study are interwoven with issues in Software, Operating system, Computer hardware and Distributed computing. His Computer architecture study incorporates themes from Compiler and Multi-core processor, Parallel computing.
The study incorporates disciplines such as Scheduling and Modulo in addition to Compiler. His Field-programmable gate array research integrates issues from Processor scheduling, Task and Circuit design. His study focuses on the intersection of Very long instruction word and fields such as Instruction set with connections in the field of Programming paradigm, Overhead and Applications architecture.
His scientific interests lie mostly in Embedded system, Electronic engineering, Computer architecture, Scaling and Electrical engineering. When carried out as part of a general Embedded system research project, his work on Reconfigurable computing, System on a chip and Field-programmable gate array is frequently linked to work in Control reconfiguration, therefore connecting diverse disciplines of study. As part of one scientific family, Diederik Verkest deals mainly with the area of Field-programmable gate array, narrowing it down to issues related to the Very long instruction word, and often Reduced instruction set computing.
His Electronic engineering study combines topics in areas such as Transistor, Node and Extreme ultraviolet lithography. His Computer architecture study combines topics from a wide range of disciplines, such as Energy consumption, Compiler and Instruction set. His research investigates the connection between Scaling and topics such as Standard cell that intersect with issues in Computer hardware.
Diederik Verkest focuses on Electronic engineering, Scaling, Electrical engineering, Node and Logic gate. His biological study spans a wide range of topics, including Nanotechnology, Interconnection and Leakage. His studies in Scaling integrate themes in fields like Optoelectronics, Stack, Standard cell and Technology scaling.
His study in Electrical engineering is interdisciplinary in nature, drawing from both Systems engineering and Silicon-germanium. As a part of the same scientific study, he usually deals with the Node, concentrating on Capacitance and frequently concerns with Line. In his work, Power performance and System requirements is strongly intertwined with Parasitic extraction, which is a subfield of Logic gate.
Electrical engineering, Electronic engineering, Scaling, Logic gate and Node are his primary areas of study. His study on Static random-access memory is often connected to Process design as part of broader study in Electronic engineering. Diederik Verkest combines subjects such as Optoelectronics, Computer hardware and Standard cell with his study of Scaling.
His Logic gate study also includes fields such as
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
ADRES: an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable Matrix
Bingfeng Mei;Serge Vernalde;Diederik Verkest;Hugo De Man.
Lecture Notes in Computer Science (2003)
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
Théodore Marescaux;Andrei Bartic;Diederik Verkest;Diederik Verkest;Serge Vernalde.
field programmable logic and applications (2002)
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling
Bingfeng Mei;S. Vernalde;D. Verkest;H. De Man.
design, automation, and test in europe (2003)
DRESC: a retargetable compiler for coarse-grained reconfigurable architectures
Bingfeng Mei;S. Vernalde;D. Verkest;H. De Man.
field-programmable technology (2002)
3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot
P. Marchal;B. Bougard;G. Katti;M. Stucchi.
Proceedings of the IEEE (2009)
Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip
J.-Y. Mignolet;V. Nollet;P. Coene;D. Verkest.
design, automation, and test in europe (2003)
Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study
Bingfeng Mei;Serge Vernalde;Diederik Verkest;Rudy Lauwereins.
design, automation, and test in europe (2004)
CoWare-a design environment for heterogeneous hardware/software systems
K. Van Rompaey;D. Verkest;I. Bolsens;H. De Man.
european design automation conference (1996)
Vertical GAAFETs for the Ultimate CMOS Scaling
Dmitry Yakimets;Geert Eneman;Pieter Schuddinck;Trong Huynh Bao.
IEEE Transactions on Electron Devices (2015)
Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles
V. Nollet;T. Marescaux;P. Avasare;D. Verkest.
design, automation, and test in europe (2005)
If you think any of the details on this page are incorrect, let us know.
We appreciate your kind effort to assist us to improve this page, it would be helpful providing us with as much detail as possible in the text box below:
KU Leuven
Imec
National University of Singapore
KU Leuven
Imec
Imec
KU Leuven
Eindhoven University of Technology
Imec
Vrije Universiteit Brussel
Utrecht University
University of Pisa
Charles River Laboratories (Netherlands)
Imperial College London
Zhejiang A & F University
Amazon (United States)
James Cook University
University of Shizuoka
University of Colorado Boulder
Cardiff University
New York University
Bar-Ilan University
University of Western Ontario
Kanazawa University
KU Leuven
Harvard University