World's Best Scientists 2026 revealed!
Rudy Lauwereins

Rudy Lauwereins

D-Index & Metrics

Computer Science

D-Index
38
Citations
6668
World Ranking
10180
National Ranking
97

Research.com Recognitions

  • 2012 - IEEE Fellow For contributions to data flow models in real-time prototyping

Overview

Rudy Lauwereins is affiliated with KU Leuven in Belgium and has contributed extensively to the field of engineering, with a specialized focus on electrical and electronic engineering. Their research spans areas including ferroelectric and negative capacitance devices, semiconductor materials and devices, advancements in semiconductor devices and circuit design, advanced memory and neural computing, radio frequency integrated circuit design, advanced neural network applications, and machine learning and extreme learning machines.

The scientist's recent published papers illustrate a strong involvement in integrated circuit design and neural network acceleration technologies. Notable publications include:

  • "84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor" (2022), IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • "OxRRAM-Based Analog in-Memory Computing for Deep Neural Network Inference: A Conductance Variability Study" (2021), IEEE Transactions on Electron Devices
  • "Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration" (2022), ACM Transactions on Design Automation of Electronic Systems
  • "System Optimization: High-Frequency Buck Converter With 3-D In-Package Air-Core Inductor" (2021), IEEE Transactions on Components Packaging and Manufacturing Technology
  • "Efficient Backside Power Delivery for High-Performance Computing Systems" (2022), IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Lauwereins has frequently published in several well-regarded venues, including:

  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • ACM Transactions on Design Automation of Electronic Systems
  • IEEE Transactions on Electron Devices
  • IEEE Transactions on Components Packaging and Manufacturing Technology

Collaboration is evident in their repeated work with several co-authors, such as Hesheng Lin, Dimitrios Velenis, Xiao Sun, Francky Catthoor, and Geert Van der Plas.

Recognized by the IEEE as a Fellow in 2012, the award cited their contributions to data flow models in real-time prototyping. This distinction reflects engagement in both theoretical and applied aspects of electronic engineering research.

Best Publications

  • Cycle-static dataflow

    G. Bilsen;M. Engels;R. Lauwereins;J. Peperstraete

  • DRESC: a retargetable compiler for coarse-grained reconfigurable architectures

    Bingfeng Mei;S. Vernalde;D. Verkest;H. De Man

  • Cyclo-static data flow

    G. Bilsen;M. Engels;R. Lauwereins;J.A. Peperstraete

  • Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling

    Bingfeng Mei;S. Vernalde;D. Verkest;H. De Man

  • Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip

    J.-Y. Mignolet;V. Nollet;P. Coene;D. Verkest

  • Architecture exploration for a reconfigurable architecture template

    Unknown

  • Grape-II: a system-level prototyping environment for DSP applications

    R. Lauwereins;M. Engels;M. Ade;J.A. Peperstraete

  • Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study

    Bingfeng Mei;Serge Vernalde;Diederik Verkest;Rudy Lauwereins

  • Designing an operating system for a heterogeneous reconfigurable SoC

    V. Nollet;P. Coene;D. Verkest;S. Vernalde

  • Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs

    Unknown

  • Reconfigurable instruction set processors from a hardware/software perspective

    F. Barat;R. Lauwereins;G. Deconinck

  • Topology adaptive network-on-chip design and implementation

    T.A. Bartic;J.-Y. Mignolet;V. Nollet;T. Marescaux

  • Managing dynamic concurrent tasks in embedded real-time multimedia systems

    Peng Yang;Paul Marchal;Chun Wong;Stefaan Himpe

  • GRAPE: a CASE tool for digital signal parallel processing

    R. Lauwereins;M. Engels;J. Peperstraete;E. Steegmans

  • A scalable 8.7nJ/bit 75.6Mb/s parallel concatenated convolutional (turbo-) CODEC

    B. Bougard;A. Giulietti;V. Derudder;J.-W. Weijers

  • Highly scalable network on chip for reconfigurable systems

    T.A. Bartic;J.-Y. Mignolet;V. Nollet;T. Marescaux

  • Run-time support for heterogeneous multitasking on reconfigurable SoCs

    T. Marescaux;V. Nollet;J.-Y. Mignolet;A. Bartic

  • SIFER: Scale-Invariant Feature Detector with Error Resilience

    Pradip Mainali;Gauthier Lafruit;Qiong Yang;Bert Geelen

  • Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates

    Halil Kukner;Seyab Khan;Pieter Weckx;Praveen Raghavan

  • Hardware-software codesign with GRAPE

    M. Ade;R. Lauwereins;J.A. Peperstraete

  • A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing

    B. Bougard;B. De Sutter;D. Verkest;L. Van der Perre

  • Enabling hardware-software multitasking on a reconfigurable computing platform for networked portable multimedia appliances

    Jean-Yves Mignolet;Serge Vernalde;Diederik Verkest;Rudy Lauwereins

  • Design, Automation, and Test in Europe

    Rudy Lauwereins;Jan Madsen

  • Proceedings of the conference on Design, automation and test in Europe

    Rudy Lauwereins;Jan Madsen

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