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Ken Takeuchi

Ken Takeuchi

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
35
Citations
8748
World Ranking
5443
National Ranking
229

Overview

Ken Takeuchi is affiliated with the University of Tokyo in Japan and has a research focus primarily in the field of Engineering, with significant contributions to Electrical and Electronic Engineering. Their work spans a range of subfields including Epidemiology, Computer Networks and Communications, Genetics, and Artificial Intelligence.

Their research covers multiple specialized topics, notably Advanced Memory and Neural Computing, Ferroelectric and Negative Capacitance Devices, Semiconductor Materials and Devices, Inflammatory Bowel Disease, Microscopic Colitis, Advanced Data Storage Technologies, and Neural Dynamics and Brain Function.

Recent publications by Ken Takeuchi illustrate a multidisciplinary approach that bridges materials science, electronics, and medical research. Recent papers include:

  • Elucidating Cathode Degradation Mechanisms in LiNi 0.8 Mn 0.1 Co 0.1 O 2 (NMC811)/Graphite Cells Under Fast Charge Rates Using Operando Synchrotron Characterization (2022, Journal of The Electrochemical Society)
  • Treatment escalation and de-escalation decisions in Crohn's disease: Delphi consensus recommendations from Japan, 2021 (2023, Journal of Gastroenterology)
  • Real-world efficacy and safety of advanced therapies in hospitalized patients with ulcerative colitis (2023, Journal of Gastroenterology)
  • A Stochastic Leaky-Integrate-and-Fire Neuron Model With Floating Gate-Based Technology for Fast and Accurate Population Coding (2022, IEEE Journal of the Electron Devices Society)
  • Privacy Protection NAND Flash System With Flexible Data-Lifetime Control by In-3-D Vertical Cell Processing (2020, IEEE Journal of Solid-State Circuits)

Ken Takeuchi frequently collaborates with other researchers, with notable coauthors including:

  • Chihiro Matsui
  • Naoko Misawa
  • Katsuyoshi Matsuoka
  • Hiroshi Nakase
  • Motohiro Esaki

Their work has been published repeatedly in several prominent venues such as:

  • Japanese Journal of Applied Physics
  • IEICE Transactions on Electronics
  • Journal of Gastroenterology
  • IEEE Journal of Solid-State Circuits
  • Gastroenterology

Best Publications

  • Organic Nonvolatile Memory Transistors for Flexible Sensor Arrays

    Tsuyoshi Sekitani;Tomoyuki Yokota;Ute Zschieschang;Hagen Klauk

  • Non-volatile semiconductor memory

    Koji Hosono;Hiroshi Nakamura;Ken Takeuchi;Kenichi Imamiya

  • Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells

    Ken Takeuchi;Tomoharu Tanaka;Noboru Shibata

  • A multipage cell architecture for high-speed programming multilevel NAND flash memories

    K. Takeuchi;T. Tanaka;T. Tanzawa

  • Nonvolatile semiconductor memory device with soft-programming to adjust erased state of memory cells

    Tomoharu Tanaka;Hiroshi Nakamura;Ken Takeuchi;Riichiro Shirota

  • Circuit techniques for a 1.8-V-only NAND flash memory

    T. Tanzawa;T. Tanaka;K. Takeuchi;H. Nakamura

  • A 56-nm CMOS 99- ${\hbox {mm}}^{2} $ 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput

    K. Takeuchi;Y. Kameda;S. Fujimura;H. Otake

  • Multi-level non-volatile semiconductor memory device with verify voltages having a smart temperature coefficient

    Ken Takeuchi;Tomoharu Tanaka

  • A double-level-V/sub th/ select gate array architecture for multilevel NAND flash memories

    K. Takeuchi;T. Tanaka;H. Nakamura

  • A 125-mm/sup 2/ 1-Gb NAND flash memory with 10-MByte/s program speed

    K. Imamiya;H. Nakamura;T. Himeno;T. Yarnamura

  • Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)

    K. Takeuchi

  • Semiconductor memory device having variable number of selected cell pages and subcell arrays

    Ken Takeuchi;Tomoharu Tanaka

  • Semiconductor memory device with test mode

    Tamio Ikehashi;Ken Takeuchi;Toshihiko Himeno

  • Nonvolatile semiconductor memory device having a data circuit for erasing and writing operations

    Ken Takeuchi;Tomoharu Tanaka

  • A compact on-chip ECC for low cost flash memories

    T. Tanzawa;T. Tanaka;K. Takeuchi;R. Shirota

  • Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs)

    Shuhei Tanakamaru;Yuki Yanagihara;Ken Takeuchi

  • A negative V/sub th/ cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories

    K. Takeuchi;S. Satoh;T. Tanaka;K. Imamiya

  • A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput

    K. Takeuchi;Y. Kameda;S. Fujimura;H. Otake

  • Memory controller and data storage device

    Ken Takeuchi;Shuhei Tanakamaru

  • x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression

    Hiroki Fujii;Kousuke Miyaji;Koh Johguchi;Kazuhide Higuchi

Frequent Co-Authors

Tomoharu Tanaka
Tomoharu Tanaka Toshiba (Japan)
Takayasu Sakurai
Takayasu Sakurai University of Tokyo
Makoto Takamiya
Makoto Takamiya University of Tokyo
Toru Tanzawa
Toru Tanzawa Shizuoka University
Jeffrey W. Lutze
Jeffrey W. Lutze Western Digital (United States)
Ute Zschieschang
Ute Zschieschang Max Planck Institute for Solid State Research
Takao Someya
Takao Someya University of Tokyo
Tsuyoshi Sekitani
Tsuyoshi Sekitani Osaka University
Tomoyuki Yokota
Tomoyuki Yokota University of Tokyo
Hagen Klauk
Hagen Klauk Max Planck Institute for Solid State Research

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